System and method for transferring data between clock domains

    公开(公告)号:GB2509375A

    公开(公告)日:2014-07-02

    申请号:GB201319714

    申请日:2013-11-08

    Applicant: IBM

    Abstract: A method for clock domain crossing is disclosed, where data is transferred from a first clock domain 160 to a second clock domain 170, wherein the second clock domain has a fixed clock frequency and the first clock domain has a variable clock frequency; the variable frequency being equal to or lower than the fixed frequency. The method comprises writing the data from the first clock domain into two buffers 110/120 connected in parallel with each other. The buffers both have time delays when transferring data from the first clock domain to the second, the time delay of the second buffer being longer than the time delay of the first buffer. The data is forwarded from the first buffer to the second clock domain when the variable frequency is equal to the fixed frequency (when in a synchronous mode), and the data is forwarded from the second buffer to the second clock domain when the variable frequency is lower than the fixed frequency (when in an asynchronous mode). The buffers may be first-in-first-out (FIFO) buffers.

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