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    Method for writing data line in cache
    1.
    发明专利
    Method for writing data line in cache 审中-公开
    在缓存中写数据线的方法

    公开(公告)号：JP2007207224A

    公开(公告)日：2007-08-16

    申请号：JP2006350532

    申请日：2006-12-26

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： JACKSON KATHRYN M ,  LANGSTON KEITH N ,  DAVID S HUTTON ,  MAK PAK-KIN ,  O'NEILL ARTHUR J JR

    IPC: G06F12/08

    CPC classification number: G06F12/0815 ,  G06F12/0811 ,  G06F2212/507

    Abstract: PROBLEM TO BE SOLVED: To provide a method for instructing an install state of a data line by using a local change bit.
    SOLUTION: A multiprocessor system is equipped with two or more individual processors, and each processor is provided with a related L1 cache. Moreover, the multiprocessor system is equipped with one or more shared main memory and one or more shared L2 cache. The method includes a step of instructing the install state of the data line by using the local change bit concerning a method of writing the data line in the L2 cache.
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种通过使用本地更改位来指示数据线的安装状态的方法。 解决方案：多处理器系统配备有两个或多个单独的处理器，并且每个处理器都提供有相关的L1高速缓存。 此外，多处理器系统配备有一个或多个共享主存储器和一个或多个共享L2高速缓存。 该方法包括通过使用关于在L2高速缓存中写入数据线的方法的本地改变位来指示数据线的安装状态的步骤。 版权所有（C）2007，JPO＆INPIT

    Multiprocessor system and method with dual system directory structure
    2.
    发明专利
    Multiprocessor system and method with dual system directory structure 有权
    具有双系统目录结构的多处理器系统和方法

    公开(公告)号：JP2007193805A

    公开(公告)日：2007-08-02

    申请号：JP2007004482

    申请日：2007-01-12

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： HUTTON DAVID S ,  WAGAR BRUCE ,  LANGSTON KEITH N ,  MAK PAK-KIN ,  JACKSON KATHRYN M

    IPC: G06F12/08

    CPC classification number: G06F12/0824

    Abstract: PROBLEM TO BE SOLVED: To provide an improved multiprocessor system and a method.
    SOLUTION: The dual system cache directory structure includes a super-set directory for cache data and a sub-set directory only for coherency control. The super-set directory and the sub-set directory have the substantially equal size, and they preferably have the size sufficient for storing all of directory entries of the processor cache as the whole. Only the super-set directory hosts the system cache data so as to back up the latest pieces of the data accessed by the processor, and the sub-set directory maintains only the removed line and the address including the address of the processor using the data. Only the directory backed up by the system cache data is rated for system cache data hitting.
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供改进的多处理器系统和方法。

    解决方案：双系统缓存目录结构包括用于高速缓存数据的超级目录和仅用于一致性控制的子集目录。 超级目录和子集目录具有基本上相同的大小，并且它们优选地具有足以存储整个处理器高速缓存的所有目录条目的大小。 只有超级目录托管系统缓存数据，以便备份处理器访问的最新数据，而子集目录仅使用数据维护处理器的行和包含处理器地址的地址 。 只有系统缓存数据备份的目录才能被系统缓存数据击中。 版权所有（C）2007，JPO＆INPIT

    HIGH SPEED REMOTE STORAGE CLUSTER INTERFACE CONTROLLER
    3.
    发明专利
    HIGH SPEED REMOTE STORAGE CLUSTER INTERFACE CONTROLLER 未知

    公开(公告)号：CA2262314C

    公开(公告)日：2002-08-13

    申请号：CA2262314

    申请日：1999-02-22

    Applicant: IBM

    Inventor： VANHUBEN GARY ALAN ,  MAK PAK-KIN ,  BLAKE MICHAEL A

    IPC: G06F12/06 ,  G06F9/50 ,  G06F12/08 ,  G06F15/17 ,  G06F15/173

    Abstract: A remote resource management system for managing resources in a symmetrical multiprocessing comprising a plurality of clusters of symmetric multiprocessors having interfaces between cluster nodes of the symmetric multiprocessor system. each cluster of the system has a local interface and interface controller. There are one or more remote storage controllers each having its local interface controller, and a local-to-remote data bus. The remote resource manager manages the interface between two clusters of symmetric multiprocessors each of which clusters has a plurality of processors, a shared cache memory, a plurality of I/O adapters and a main memory accessible from the cluster. This remote resource manager manages resources with a remote storage controller to distribute work to a remote controller acting as an agent to perform a desir ed operation without requiring knowledge of a requestor who initiated the work request. Said work is transferred only when a remote requestor is available for processing of the work, without a need for constant communication between the clusters of symmetric multiprocessors.

    System and method of low latency data tranfer between clock domains operated in various synchronization modes
    4.
    发明专利
    System and method of low latency data tranfer between clock domains operated in various synchronization modes 未知

    公开(公告)号：GB2513529A

    公开(公告)日：2014-11-05

    申请号：GB201220534

    申请日：2012-11-15

    Applicant: IBM

    Inventor： HARRER HUBERT ,  DREPS DANIEL M ,  FERRAIOLO FRANK D ,  WEBEL TOBIAS ,  WEISS ULRICH ,  TONG CHING-LUNG L ,  MAK PAK-KIN

    IPC: G06F1/12 ,  G06F1/08 ,  G06F13/40

    Abstract: A method for clock domain crossing is disclosed, where data is transferred from a first clock domain 160 to a second clock domain 170, wherein the second clock domain has a fixed clock frequency and the first clock domain has a variable clock frequency, the variable frequency being equal to or lower than the fixed frequency. The method comprises writing the data from the first clock domain into two buffers 110/120 connected in parallel with each other. The buffers both have time delays when transferring data from the first clock domain to the second, the time delay of the second buffer being longer than the time delay of the first buffer. The data is forwarded from the first buffer to the second clock domain when the variable frequency is equal to the fixed frequency (when in a synchronous mode), and the data is forwarded from the second buffer to the second clock domain when the variable frequency is lower than the fixed frequency (when in an asynchronous mode). The buffers may be first-in-first-out (FIFO) buffers.

    HIGH SPEED REMOTE STORAGE CLUSTER INTERFACE CONTROLLER
    6.
    发明专利
    HIGH SPEED REMOTE STORAGE CLUSTER INTERFACE CONTROLLER 未知

    公开(公告)号：CA2262314A1

    公开(公告)日：1999-09-23

    申请号：CA2262314

    申请日：1999-02-22

    Applicant: IBM

    Inventor： VANHUBEN GARY ALAN ,  MAK PAK-KIN ,  BLAKE MICHAEL A

    IPC: G06F12/06 ,  G06F9/50 ,  G06F12/08 ,  G06F15/17 ,  G06F15/173

    Abstract: A remote resource management system for managing resources in a symmetrical multiprocessing comprising a plurality of clusters of symmetric multiprocessors having interfaces between cluster nodes of the symmetric multiprocessor system. each cluster of the system has a local interface and interface controller. There are one or more remote storage controllers each having its local interface controller, and a local-to-remote data bus. The remote resource manager manages the interface between two clusters of symmetric multiprocessors each of which clusters has a plurality of processors, a shared cache memory, a plurality of I/O adapters and a main memory accessible from the cluster. This remote resource manager manages resources with a remote storage controller to distribute work to a remote controller acting as an agent to perform a desired operation without requiring knowledge of a requestor who initiated the work request. Said work is transferred only when a remote requestor is available for processing of the work, without a need for constant communication between the clusters of symmetric multiprocessors.

    System and method for transferring data between clock domains
    7.
    发明专利
    System and method for transferring data between clock domains 未知

    公开(公告)号：GB2509375A

    公开(公告)日：2014-07-02

    申请号：GB201319714

    申请日：2013-11-08

    Applicant: IBM

    Inventor： HARPER HUBERT ,  DREPS DANIEL ,  FERRAIOLO FRANK ,  WEBEL TOBIAS ,  WEISS ULRICH ,  TONG CHING-LUNG L ,  MAK PAK-KIN

    IPC: G06F1/12 ,  G06F1/08 ,  G06F13/40

    Abstract: A method for clock domain crossing is disclosed, where data is transferred from a first clock domain 160 to a second clock domain 170, wherein the second clock domain has a fixed clock frequency and the first clock domain has a variable clock frequency; the variable frequency being equal to or lower than the fixed frequency. The method comprises writing the data from the first clock domain into two buffers 110/120 connected in parallel with each other. The buffers both have time delays when transferring data from the first clock domain to the second, the time delay of the second buffer being longer than the time delay of the first buffer. The data is forwarded from the first buffer to the second clock domain when the variable frequency is equal to the fixed frequency (when in a synchronous mode), and the data is forwarded from the second buffer to the second clock domain when the variable frequency is lower than the fixed frequency (when in an asynchronous mode). The buffers may be first-in-first-out (FIFO) buffers.

    9.
    发明专利
    未知

    公开(公告)号：AT502336T

    公开(公告)日：2011-04-15

    申请号：AT07857301

    申请日：2007-12-07

    Applicant: IBM

    Inventor： CLARK LEO ,  FIELDS JR JAMES STEPHEN ,  MAK PAK-KIN ,  STARKE WILLIAM JOHN

    IPC: G06F12/08

    Abstract: A system and method for implementing an enhanced hover state with active prefetches. According to a preferred embodiment of the present invention, a snooper in a processing unit receives a system-wide update complete operation indicating a completion of a storage-modifying operation targeting a particular address, where the storage-modifying operation results in a modified first cache line in a first cache memory. The snooper determines if a second cache memory held a second cache line associated with the particular address prior to receiving the system-wide update complete operation. If so, the snooper issues a prefetch request for a copy of the modified first cache line to replace the second cache line in the second cache memory. The snooper updates the second cache memory with a copy of the modified first cache line.

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