公开(公告)号：DE68916784D1

公开(公告)日：1994-08-18

申请号：DE68916784

申请日：1989-04-20

Applicant: IBM

Inventor： SCHETTLER HELMUT DIPL ING ,  LUDWIG THOMAS DIPL ING ,  WAGNER OTTO M DIPL-ING ,  HAUG WERNER O DIPL ING ,  KLINK ERICH ,  KROELL KARL E DIPL-PHYS ,  STAHL RAINER DIPL ING

IPC: H01L21/60 ,  H01L23/14 ,  H01L23/64

Abstract: Integrated circuit package comprising at least one active integrated circuit chip (1) mounted and electrically connected to a power supply distribution wiring and a chip interconnection and signal wiring both formed on the topsurface of a passive semiconductor interconnection carrier (2) in which a power supply decoupling capacitor is implemented. Spaced wells (4) of a first conductivity type are provided in the surface of said carrier of a second conductivity type. The power supply distribution wiring comprises first and second conductive lines (5, 6) within a first wiring level (WL1). Said first conductive lines (5) are deposited on the surface areas of said wells (4) in an ohmic contact relationship and said second conductive lines (6) are deposited on the surface areas of said carrier (2) between said wells (4) in an ohmic contact relationship. Said first and second conductive lines are connected to first and second terminals of the power supply, respectively, so that the junction capacitance between said wells (4) and the carrier material (2) embedding said wells forms said decoupling capacitor.

公开(公告)号：DE68916784T2

公开(公告)日：1995-01-05

申请号：DE68916784

申请日：1989-04-20

Applicant: IBM

Inventor： SCHETTLER HELMUT DIPL ING ,  LUDWIG THOMAS DIPL ING ,  WAGNER OTTO M DIPL-ING ,  HAUG WERNER O DIPL ING ,  KLINK ERICH ,  KROELL KARL E DIPL-PHYS ,  STAHL RAINER DIPL ING

IPC: H01L21/60 ,  H01L23/14 ,  H01L23/64

Abstract: Integrated circuit package comprising at least one active integrated circuit chip (1) mounted and electrically connected to a power supply distribution wiring and a chip interconnection and signal wiring both formed on the topsurface of a passive semiconductor interconnection carrier (2) in which a power supply decoupling capacitor is implemented. Spaced wells (4) of a first conductivity type are provided in the surface of said carrier of a second conductivity type. The power supply distribution wiring comprises first and second conductive lines (5, 6) within a first wiring level (WL1). Said first conductive lines (5) are deposited on the surface areas of said wells (4) in an ohmic contact relationship and said second conductive lines (6) are deposited on the surface areas of said carrier (2) between said wells (4) in an ohmic contact relationship. Said first and second conductive lines are connected to first and second terminals of the power supply, respectively, so that the junction capacitance between said wells (4) and the carrier material (2) embedding said wells forms said decoupling capacitor.