-
公开(公告)号：DE3310691A1
公开(公告)日：1984-09-27
申请号：DE3310691
申请日：1983-03-24
Applicant: IBM DEUTSCHLAND
Inventor： STADLER EWALD , WAGNER OTTO DIPL ING , GRUBER HARALD , STAHL RAINER DIPL ING
Abstract: The invention relates to a socket plate for a plug-in connection between a circuit board which is provided with plug pins and a printed circuit, and a circuit module which is provided with plug pins and has an upper and a lower covering plate and a plate which is located between them, is provided with resilient contacts in a sprung manner and is characterised in that it consists of an elastomeric material and has a matrix-like arrangement of continuous slots (7) which lie in rows and columns, in that the cover plates (9, 10) have an identical arrangement of outwardly inclined openings (2), and in that the side walls of the slots and the inclined surfaces of the openings have metallic contact strips (8) resting thereon, and in that this socket plate is held by means of an elastic frame which engages around the edges.
-
公开(公告)号：DE68916784D1
公开(公告)日：1994-08-18
申请号：DE68916784
申请日：1989-04-20
Applicant: IBM
Inventor： SCHETTLER HELMUT DIPL ING , LUDWIG THOMAS DIPL ING , WAGNER OTTO M DIPL-ING , HAUG WERNER O DIPL ING , KLINK ERICH , KROELL KARL E DIPL-PHYS , STAHL RAINER DIPL ING
Abstract: Integrated circuit package comprising at least one active integrated circuit chip (1) mounted and electrically connected to a power supply distribution wiring and a chip interconnection and signal wiring both formed on the topsurface of a passive semiconductor interconnection carrier (2) in which a power supply decoupling capacitor is implemented. Spaced wells (4) of a first conductivity type are provided in the surface of said carrier of a second conductivity type. The power supply distribution wiring comprises first and second conductive lines (5, 6) within a first wiring level (WL1). Said first conductive lines (5) are deposited on the surface areas of said wells (4) in an ohmic contact relationship and said second conductive lines (6) are deposited on the surface areas of said carrier (2) between said wells (4) in an ohmic contact relationship. Said first and second conductive lines are connected to first and second terminals of the power supply, respectively, so that the junction capacitance between said wells (4) and the carrier material (2) embedding said wells forms said decoupling capacitor.
-
公开(公告)号：DE68916784T2
公开(公告)日：1995-01-05
申请号：DE68916784
申请日：1989-04-20
Applicant: IBM
Inventor： SCHETTLER HELMUT DIPL ING , LUDWIG THOMAS DIPL ING , WAGNER OTTO M DIPL-ING , HAUG WERNER O DIPL ING , KLINK ERICH , KROELL KARL E DIPL-PHYS , STAHL RAINER DIPL ING
Abstract: Integrated circuit package comprising at least one active integrated circuit chip (1) mounted and electrically connected to a power supply distribution wiring and a chip interconnection and signal wiring both formed on the topsurface of a passive semiconductor interconnection carrier (2) in which a power supply decoupling capacitor is implemented. Spaced wells (4) of a first conductivity type are provided in the surface of said carrier of a second conductivity type. The power supply distribution wiring comprises first and second conductive lines (5, 6) within a first wiring level (WL1). Said first conductive lines (5) are deposited on the surface areas of said wells (4) in an ohmic contact relationship and said second conductive lines (6) are deposited on the surface areas of said carrier (2) between said wells (4) in an ohmic contact relationship. Said first and second conductive lines are connected to first and second terminals of the power supply, respectively, so that the junction capacitance between said wells (4) and the carrier material (2) embedding said wells forms said decoupling capacitor.
-
-
Search Results
3
records
(took 0.016 seconds)
