公开(公告)号：JPH10188554A

公开(公告)日：1998-07-21

申请号：JP30702997

申请日：1997-11-10

Applicant: IBM

Inventor： CONNOLLY BRIAN J ,  DELL TIMOTHY JAY ,  HAZELZET BRUCE GERARD ,  KELLOGG MARK WILLIAM

IPC: G11C11/406 ,  G11C11/401 ,  G11C11/407

Abstract: PROBLEM TO BE SOLVED: To make both CBR and hidden refreshing executable on a DRAM forming a SIMM or a DIMM, by converting each one system RAS and CAS signal into a plurality of RAS and CAS signals for normal read/write operation on the DRAM. SOLUTION: An ASIC chip 78 converts a SYS-RAS signal into RAS-T or RAS-B signals by a signal of a pin A12 or an SYS-CAS signal to CAS-L or CAS-R signals using an address on a pin A10 separately. A RAS sample latch 90 determines whether the cycle corresponds to CBR or not by a signal from a receiver 80 to perform a CBR refreshing or a normal reading/writing. An RAS address latch 92 and a CAS sample latch 96 determine a hidden refreshing by signals from receivers 82 and 84 and an inverter 94 to execute. This accomplishes both of the CBR and the hidden refreshing on a DRAM.