公开(公告)号：US3785886A

公开(公告)日：1974-01-15

申请号：US11753471

申请日：1971-02-22

Applicant: IBM

Inventor： CASTRUCCI P ,  GROCHOWSKI E ,  HESS M ,  MAHERAS G ,  NORTH W

IPC: H01L21/00 ,  H01L21/761 ,  H01L21/8222 ,  H01L29/00 ,  H01L7/36 ,  H01L19/00

CPC classification number: H01L21/00 ,  H01L21/761 ,  H01L21/8222 ,  H01L29/00 ,  Y10S148/037 ,  Y10S148/085 ,  Y10S148/115 ,  Y10S438/91

Abstract: A method for fabricating a semiconductor device which is composed of a monocrystalline semiconductor body having a surface crystallographic orientation substantially parallel to a plane and having a PN junction formed in the body. The body has an insulator coating, such as silicon dioxide, over the PN junction. The surface state density at the semiconductorinsulator interface is very low. This low density is believed to be a reason for the increased beta in the oriented material semiconductor device. Further, the device has a low defect density and few dopant precipitate sites even at high dopant levels. A monolithic integrated circuit structure composed of the monocrystalline semiconductor substrate having a surface crystallographic orientation substantially parallel to a plane with a plurality of semiconductor devices within the substrate is described. The devices may be isolated from one another by PN junctions. The tolerance in a given isolated device, between the PN junction and the nearest region having a different conductivity is less then approximately 0.3 mils. This very close spacing allows substantially greater compactness of semiconductor devices within a monocrystalline semiconductor body than has ever been previously accomplished.

公开(公告)号：US3723200A

公开(公告)日：1973-03-27

申请号：US3723200D

申请日：1970-01-26

Applicant: IBM

Inventor： CASTRUCCI P ,  GROCHOWSKI E ,  HESS M ,  ZACHOS E

IPC: H01L21/761 ,  H01L7/00 ,  H01L19/00

CPC classification number: H01L21/761 ,  Y10S148/037 ,  Y10S148/085 ,  Y10S148/145

Abstract: A MONOLITHIC MICROCIRCUIT FABRICATION METHOD EMPLOYING AN OPTIMIZED MIDDLE ISOLATION TECHNIQUE FOR PRODUCING SPECIFIC VERTICAL DIFFUSION WALLS OF MINIMUM CRITICAL HORIZONTAL DIMENSIONS IS DISCLOSED TO FACILITATE MAXIMUM DENSITY OF ELECTRICALLY ISOLATED MICROCIRCUIT COMPONENTS. A FIRST EPITAXIAL LAYER IS GROWN ON A SEMICONDUCTOR SUBTRATE AND REGIONS OF ISOLATION IMPURITIES ARE PLACED THEREIN AT DESIRED LOCATIONS. A SECOND EPITAXIAL LAYER IS GROWN OVER THE FIRST EPITAXIAL LAYER (WHILE THE IMPURITIES OUT-DIFFUSE INTO BOTH EPITAXIAL LAYERS) UNTIL THE NON-ISOLATES THICKNESS REMAINING IN THE FIRST EPITAXIAL LAYER BECOMES EQUAL TO THE NON-ISOLATED THICKNESS REMAINING IN THE SECOND EPITAXIAL LAYER. SUBSEQUENT CONVENTIONAL HEAT TREATMENT STEPS SUCH AS ARE REQUIRED FOR THE OXIDATION AND DIFFUSION CYCLES OF TYPICAL MICROCIRCUIT COMPONENTS CONTINUE THE OUT-DIFFUSION OF THE IMPURITY REGIONS SO AS TO FORM COMPLETED VERTICAL ISOLATION WALLS BETWEEN SAID COMPONENTS.

D R A W I N G

公开(公告)号：SE352781B

公开(公告)日：1973-01-08

申请号：SE1394768

申请日：1968-10-16

Applicant: IBM

Inventor： CASTRUCCI P ,  GROCHOWSKI E ,  HESS M ,  MAHERAS G ,  NORTH W

IPC: H01L21/822 ,  H01L21/331 ,  H01L21/74 ,  H01L21/8222 ,  H01L27/00 ,  H01L27/04 ,  H01L29/04 ,  H01L29/73 ,  H01L19/00

Abstract: 1,241,057. Semi-conductor devices. INTERNATIONAL BUSINESS MACHINES CORP. 2 Oct., 1968 [19 Oct., 1967], No. 46759/68. Heading H1K. A high conductivity N type zone in a device formed in a body of monocrystalline semiconductor material having a face parallel to a 100 crystallographic plane has a surface concentration of phosphorus of 2À5 to 4 x 10 3 parts per million by weight. This is achieved without significant precipitation of phosphorus due to the low dislocation density in thus aligned material. A junction isolated transistor (Fig. 2) in a typical solid circuit embodiment is formed on a 10-20 ohm. cm. P type silicon wafer 30 cut from a crystal grown along a 100 axis with its faces in a 100 plane. Subcollector region 32 is formed by diffusion and extends during epitaxial deposition of N-type epitaxial layer 34. A grid of isolation walls 37 is next diffused in prior to formation of base 38 and emitter 40 by successive diffusions. Alternatively region 32 is formed by ion implantation or etch and refill steps. Aluminium, platinum or palladium contacts 42 are formed by vapour deposition overall followed by pattern etching in a nitric-phosphoric acid mix. The diffusions are all effected through holes formed by conventional photolithographic techniques in thermal oxide layers. Arsenic is the dopant in regions 32, 34, boron in 37, 38 and phosphorus in the collector. The decline in current gain # with falling collector current is far less than in an otherwise identical device formed on a 111 orientated substrate. Manufacture of an oxide or nitride passivated planar epitaxial transistor (Fig. 1, not shown) with a phosphorus doped emitter and of an enhancement mode IGFET with N+ phosphorus doped source and drain regions is also described. The IGFET has a lower threshold voltage than its 111 orientated counterpart.