公开(公告)号：US3801836A

公开(公告)日：1974-04-02

申请号：US3801836D

申请日：1972-01-07

Applicant: IBM

Inventor： CASTRUCCI P ,  GROCHOWSKI E ,  NORTH W ,  PALFI T

IPC: F16N27/00 ,  H01L21/761 ,  H01L23/535 ,  H01L27/00 ,  H01L27/102 ,  H01L29/417 ,  H01L19/00

CPC classification number: H01L29/41708 ,  F16N27/00 ,  H01L21/761 ,  H01L23/535 ,  H01L27/00 ,  H01L27/1025 ,  H01L2924/0002 ,  Y10S148/037 ,  Y10S148/049 ,  Y10S148/085 ,  Y10S148/151 ,  H01L2924/00

Abstract: A planar integrated semiconductor circuit having common emitter transistor elements isolated from each other and from other transistors by the emitter regions which form a PN or rectifying junction with the body of the semiconductor member in which the integrated circuit is formed. In a semiconductor member or body of one type conductivity, a plurality of emitter regions of opposite type conductivity extend from one planar surface of the body. One or more of the emitter regions each have a plurality of discrete base regions of the one type conductivity extending from said planar surface fully enclosed within the emitter region. Each of the base regions in turn has at least one collector region enclosed within it at the planar surface. The emitter region has a higher majority carrier concentration than the majority carrier concentration within its enclosed base regions. The rectifying junction formed by the opposite conductivity emitter region with the one type conductivity semiconductor body serves to isolate the emitter regions from each other.

Abstract translation: 一种平面集成半导体电路，具有通过与其中形成集成电路的半导体部件的主体形成PN或整流的发射极区彼此隔离并与其它晶体管隔离的共同发射极晶体管元件。 在一种导电类型的半导体部件或本体中，具有相反导电性的多个发射极区从主体的一个平面延伸。 一个或多个发射极区域各自具有从完全封装在发射极区域内的所述平坦表面延伸的一种类型电导率的多个离散基极区域。 每个基本区域依次具有在平坦表面处封装在其内的至少一个收集器区域。 发射极区域具有比其封闭的基极区域内的多数载流子浓度更高的载流子浓度。 由相反的导电性发射极区域与一个导电型半导体体形成的整流用于隔离发射极区域。

公开(公告)号：US3785886A

公开(公告)日：1974-01-15

申请号：US11753471

申请日：1971-02-22

Applicant: IBM

Inventor： CASTRUCCI P ,  GROCHOWSKI E ,  HESS M ,  MAHERAS G ,  NORTH W

IPC: H01L21/00 ,  H01L21/761 ,  H01L21/8222 ,  H01L29/00 ,  H01L7/36 ,  H01L19/00

CPC classification number: H01L21/00 ,  H01L21/761 ,  H01L21/8222 ,  H01L29/00 ,  Y10S148/037 ,  Y10S148/085 ,  Y10S148/115 ,  Y10S438/91

Abstract: A method for fabricating a semiconductor device which is composed of a monocrystalline semiconductor body having a surface crystallographic orientation substantially parallel to a plane and having a PN junction formed in the body. The body has an insulator coating, such as silicon dioxide, over the PN junction. The surface state density at the semiconductorinsulator interface is very low. This low density is believed to be a reason for the increased beta in the oriented material semiconductor device. Further, the device has a low defect density and few dopant precipitate sites even at high dopant levels. A monolithic integrated circuit structure composed of the monocrystalline semiconductor substrate having a surface crystallographic orientation substantially parallel to a plane with a plurality of semiconductor devices within the substrate is described. The devices may be isolated from one another by PN junctions. The tolerance in a given isolated device, between the PN junction and the nearest region having a different conductivity is less then approximately 0.3 mils. This very close spacing allows substantially greater compactness of semiconductor devices within a monocrystalline semiconductor body than has ever been previously accomplished.

公开(公告)号：SE366864B

公开(公告)日：1974-05-06

申请号：SE1253370

申请日：1970-09-15

Applicant: IBM

Inventor： CASTRUCCI P ,  GATES H ,  HENLE R ,  PRICER W ,  MORTON R ,  MASON J ,  NORTH W

IPC: F22B21/06 ,  G11C17/06 ,  G11C17/14 ,  G11C17/16 ,  H01L23/525 ,  H01L27/00 ,  H01L27/102 ,  G11C17/00

Abstract: A read only memory having the capability of being written into once after manufacture. The cells of the memory are capable of being fused or permanently altered by directing a fusing current to the selected cells. The cell is a monolithic semiconductor device comprising a diode to be biased in a forward direction and a diode to be biased in the reverse direction structured so as to form back-to-back diodes. The reverse diode has a lower reverse breakdown voltage than the forward diode, and a metal connection, unconnected to any remaining circuit elements contacts the semiconductor device between diode junctions. The fusing current causes a metal-semiconductor alloy to form and short out the reverse diode.

公开(公告)号：CA935919A

公开(公告)日：1973-10-23

申请号：CA158250

申请日：1972-12-05

Applicant: IBM

Inventor： MORTON R ,  PRICER W ,  GATES H ,  HENLE R ,  NORTH W ,  CASTRUCCI P ,  MASON J

公开(公告)号：SE352781B

公开(公告)日：1973-01-08

申请号：SE1394768

申请日：1968-10-16

Applicant: IBM

Inventor： CASTRUCCI P ,  GROCHOWSKI E ,  HESS M ,  MAHERAS G ,  NORTH W

IPC: H01L21/822 ,  H01L21/331 ,  H01L21/74 ,  H01L21/8222 ,  H01L27/00 ,  H01L27/04 ,  H01L29/04 ,  H01L29/73 ,  H01L19/00

Abstract: 1,241,057. Semi-conductor devices. INTERNATIONAL BUSINESS MACHINES CORP. 2 Oct., 1968 [19 Oct., 1967], No. 46759/68. Heading H1K. A high conductivity N type zone in a device formed in a body of monocrystalline semiconductor material having a face parallel to a 100 crystallographic plane has a surface concentration of phosphorus of 2À5 to 4 x 10 3 parts per million by weight. This is achieved without significant precipitation of phosphorus due to the low dislocation density in thus aligned material. A junction isolated transistor (Fig. 2) in a typical solid circuit embodiment is formed on a 10-20 ohm. cm. P type silicon wafer 30 cut from a crystal grown along a 100 axis with its faces in a 100 plane. Subcollector region 32 is formed by diffusion and extends during epitaxial deposition of N-type epitaxial layer 34. A grid of isolation walls 37 is next diffused in prior to formation of base 38 and emitter 40 by successive diffusions. Alternatively region 32 is formed by ion implantation or etch and refill steps. Aluminium, platinum or palladium contacts 42 are formed by vapour deposition overall followed by pattern etching in a nitric-phosphoric acid mix. The diffusions are all effected through holes formed by conventional photolithographic techniques in thermal oxide layers. Arsenic is the dopant in regions 32, 34, boron in 37, 38 and phosphorus in the collector. The decline in current gain # with falling collector current is far less than in an otherwise identical device formed on a 111 orientated substrate. Manufacture of an oxide or nitride passivated planar epitaxial transistor (Fig. 1, not shown) with a phosphorus doped emitter and of an enhancement mode IGFET with N+ phosphorus doped source and drain regions is also described. The IGFET has a lower threshold voltage than its 111 orientated counterpart.