公开(公告)号：US3731375A

公开(公告)日：1973-05-08

申请号：US3731375D

申请日：1970-04-16

Applicant: IBM

Inventor： AGUSTA B ,  BARDELL P ,  CASTRUCCI P ,  HENLE R ,  PECORATO R

IPC: G11C11/411 ,  H03K3/286 ,  H03K3/288 ,  B01J17/00 ,  H01L1/16

CPC classification number: H03K3/286 ,  G11C11/4113 ,  H03K3/288 ,  Y10S438/917

Abstract: A method of making a monolithic integrated semiconductor structure that has a plurality of functionally isolated individual cells that are electrically interconnected. Each of the cells is an object of mirror image cell that is vertically, horizontally and diagonally displaced from the object cell. The plurality of cells provide a memory array with electrical components of each memory cell composed of active and passive semiconductor devices. Other importance aspects of the structure include underpass connections and active devices in a common portion of the structure which are electrically interconnected at the same node potential by means of a highly doped buried region within the common portion of the structure.

Abstract translation: 一种制造单片集成半导体结构的方法，其具有电互连的多个功能隔离的单个电池。 每个单元是从对象单元垂直，水平和对角地移位的镜像单元的对象。 多个单元提供具有由有源和无源半导体器件组成的每个存储单元的电气部件的存储器阵列。 该结构的其他重要方面包括在结构的公共部分中的地下通道连接和有源器件，其通过在结构的公共部分内的高掺杂掩埋区在相同的节点电位电互连。

公开(公告)号：US3766438A

公开(公告)日：1973-10-16

申请号：US3766438D

申请日：1970-05-26

Applicant: IBM

Inventor： CASTRUCCI P ,  MASON J

IPC: H01L21/306 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L19/00

CPC classification number: H01L21/31111 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/31055 ,  H01L21/76297 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/106 ,  Y10S438/945 ,  Y10S438/977

Abstract: A method for fabricating dielectric isolated integrated devices which allows the formation of a truly planar surface. The method includes etching isolation channels in a semiconductor substrate through a suitable mask. The mask pattern is designed to enhance deeper etching at certain locations in the isolation channels. A dielectric layer is formed over the exposed surfaces of the isolation channels and a semiconductor material is grown in the channels. The deeper etched locations which are now filled with dielectric isolation are used as a depth guide in the formation of a dielectric layer from the semiconductor substrate surface opposite to the one from which the etching took place. The depth guide can be used in either a deep etch or lap-back process. The last isolation step is then to continue the dielectric layer past the depth guide to the major portion of the isolation channels to produce the fully isolated islands of semiconductor material in the semiconductor substrate.

公开(公告)号：US3823348A

公开(公告)日：1974-07-09

申请号：US3311970

申请日：1970-04-16

Applicant: IBM

Inventor： CASTRUCCI P ,  HENLE R ,  AGUSTA B ,  BARDELL P ,  PECORARO R

IPC: G11C11/411 ,  H03K3/286 ,  H03K3/288 ,  H01L5/00

CPC classification number: H03K3/286 ,  G11C11/4113 ,  H03K3/288

Abstract: A monolithic integrated semiconductor structure is described that has a plurality of functionally isolated individual cells that are electrically interconnected. Each of the cells is an object or mirror image cell that is vertically, horizontally and diagonally displaced from the object cell. The plurality of cells provide a memory array with electrical components of each memory cell composed of active and passive semiconductor devices. Other important aspects of the structure include underpass connections and active devices in a common portion of the structure which are electrically interconnected at the same node potential by means of a highly doped buried region within the common portion of the structure. In particular, a sophisticated packaging scheme for containing such a highly complex array of memory cells is disclosed.

公开(公告)号：US3729316A

公开(公告)日：1973-04-24

申请号：US3729316D

申请日：1970-02-17

Applicant: IBM

Inventor： PECORARO R ,  CASTRUCCI P ,  HADDAD N

IPC: H05K3/00 ,  G03F1/00 ,  H01L21/00 ,  H01L21/027 ,  G03C5/00

CPC classification number: G03F1/60 ,  H01L21/00

Abstract: A PROCESS FOR MAKING A PHOTOGRAPHIC OPTICAL GLASS MASK THAT IS USED IN SILICON INTEGRAED CIRCUIT WAFER PROCESSING. AN OPTICAL GLASS MASK IS MADE BY MEANS OF A STEP AND REPEAT CAMERA. DISPLACEMENT ERROR WHICH IS CAUSED BY THE DIFFERENCE IN CEFFICIENTS OF EXPANSION BETWEEN THE MICROSET SCALE OF THE STEP AND REPEAT CAMERA AND THE PHOTOGRAPHIC OPTICAL MASK, IS MINIMIZED BY USING THE SAME MATERIAL FOR BOTH ELEMENTS. FURTHER DISPLACEMENT ERROR CAUSED BY THERMAL MISMATCH OF THE OPTICAL GLASS MASK AND THE SILICON WAFER IS MINIMIZED BY USING A BOROSILICATE GLASS MASK HAVING A LINEAR COEFFICIENT OF EXPANSION OF 3.5X10-6/DEGREES C., WHICH SUBSTANTIALLY MATCHES HE LINEAR COEFFICIENT OF EXPANSION OF THE SILICON WAFER MATERIAL.

Abstract translation: 1323647 Photo-masks国际商业公司1971年4月19日[1970年2月17日] 21760/71标题G2M制备半导体集成电路的光掩模包括布置在硼硅酸盐玻璃支撑构件上的电路图案。 主面罩可以通过步骤和重复照相机制成，并用于联系打印副主席，后者又用于联系打印工作台面具，2个主人和面具都有硼硅酸盐玻璃支架。

公开(公告)号：US3801836A

公开(公告)日：1974-04-02

申请号：US3801836D

申请日：1972-01-07

Applicant: IBM

Inventor： CASTRUCCI P ,  GROCHOWSKI E ,  NORTH W ,  PALFI T

IPC: F16N27/00 ,  H01L21/761 ,  H01L23/535 ,  H01L27/00 ,  H01L27/102 ,  H01L29/417 ,  H01L19/00

CPC classification number: H01L29/41708 ,  F16N27/00 ,  H01L21/761 ,  H01L23/535 ,  H01L27/00 ,  H01L27/1025 ,  H01L2924/0002 ,  Y10S148/037 ,  Y10S148/049 ,  Y10S148/085 ,  Y10S148/151 ,  H01L2924/00

Abstract: A planar integrated semiconductor circuit having common emitter transistor elements isolated from each other and from other transistors by the emitter regions which form a PN or rectifying junction with the body of the semiconductor member in which the integrated circuit is formed. In a semiconductor member or body of one type conductivity, a plurality of emitter regions of opposite type conductivity extend from one planar surface of the body. One or more of the emitter regions each have a plurality of discrete base regions of the one type conductivity extending from said planar surface fully enclosed within the emitter region. Each of the base regions in turn has at least one collector region enclosed within it at the planar surface. The emitter region has a higher majority carrier concentration than the majority carrier concentration within its enclosed base regions. The rectifying junction formed by the opposite conductivity emitter region with the one type conductivity semiconductor body serves to isolate the emitter regions from each other.

Abstract translation: 一种平面集成半导体电路，具有通过与其中形成集成电路的半导体部件的主体形成PN或整流的发射极区彼此隔离并与其它晶体管隔离的共同发射极晶体管元件。 在一种导电类型的半导体部件或本体中，具有相反导电性的多个发射极区从主体的一个平面延伸。 一个或多个发射极区域各自具有从完全封装在发射极区域内的所述平坦表面延伸的一种类型电导率的多个离散基极区域。 每个基本区域依次具有在平坦表面处封装在其内的至少一个收集器区域。 发射极区域具有比其封闭的基极区域内的多数载流子浓度更高的载流子浓度。 由相反的导电性发射极区域与一个导电型半导体体形成的整流用于隔离发射极区域。

公开(公告)号：US3785886A

公开(公告)日：1974-01-15

申请号：US11753471

申请日：1971-02-22

Applicant: IBM

Inventor： CASTRUCCI P ,  GROCHOWSKI E ,  HESS M ,  MAHERAS G ,  NORTH W

IPC: H01L21/00 ,  H01L21/761 ,  H01L21/8222 ,  H01L29/00 ,  H01L7/36 ,  H01L19/00

CPC classification number: H01L21/00 ,  H01L21/761 ,  H01L21/8222 ,  H01L29/00 ,  Y10S148/037 ,  Y10S148/085 ,  Y10S148/115 ,  Y10S438/91

Abstract: A method for fabricating a semiconductor device which is composed of a monocrystalline semiconductor body having a surface crystallographic orientation substantially parallel to a plane and having a PN junction formed in the body. The body has an insulator coating, such as silicon dioxide, over the PN junction. The surface state density at the semiconductorinsulator interface is very low. This low density is believed to be a reason for the increased beta in the oriented material semiconductor device. Further, the device has a low defect density and few dopant precipitate sites even at high dopant levels. A monolithic integrated circuit structure composed of the monocrystalline semiconductor substrate having a surface crystallographic orientation substantially parallel to a plane with a plurality of semiconductor devices within the substrate is described. The devices may be isolated from one another by PN junctions. The tolerance in a given isolated device, between the PN junction and the nearest region having a different conductivity is less then approximately 0.3 mils. This very close spacing allows substantially greater compactness of semiconductor devices within a monocrystalline semiconductor body than has ever been previously accomplished.

公开(公告)号：US3723200A

公开(公告)日：1973-03-27

申请号：US3723200D

申请日：1970-01-26

Applicant: IBM

Inventor： CASTRUCCI P ,  GROCHOWSKI E ,  HESS M ,  ZACHOS E

IPC: H01L21/761 ,  H01L7/00 ,  H01L19/00

CPC classification number: H01L21/761 ,  Y10S148/037 ,  Y10S148/085 ,  Y10S148/145

Abstract: A MONOLITHIC MICROCIRCUIT FABRICATION METHOD EMPLOYING AN OPTIMIZED MIDDLE ISOLATION TECHNIQUE FOR PRODUCING SPECIFIC VERTICAL DIFFUSION WALLS OF MINIMUM CRITICAL HORIZONTAL DIMENSIONS IS DISCLOSED TO FACILITATE MAXIMUM DENSITY OF ELECTRICALLY ISOLATED MICROCIRCUIT COMPONENTS. A FIRST EPITAXIAL LAYER IS GROWN ON A SEMICONDUCTOR SUBTRATE AND REGIONS OF ISOLATION IMPURITIES ARE PLACED THEREIN AT DESIRED LOCATIONS. A SECOND EPITAXIAL LAYER IS GROWN OVER THE FIRST EPITAXIAL LAYER (WHILE THE IMPURITIES OUT-DIFFUSE INTO BOTH EPITAXIAL LAYERS) UNTIL THE NON-ISOLATES THICKNESS REMAINING IN THE FIRST EPITAXIAL LAYER BECOMES EQUAL TO THE NON-ISOLATED THICKNESS REMAINING IN THE SECOND EPITAXIAL LAYER. SUBSEQUENT CONVENTIONAL HEAT TREATMENT STEPS SUCH AS ARE REQUIRED FOR THE OXIDATION AND DIFFUSION CYCLES OF TYPICAL MICROCIRCUIT COMPONENTS CONTINUE THE OUT-DIFFUSION OF THE IMPURITY REGIONS SO AS TO FORM COMPLETED VERTICAL ISOLATION WALLS BETWEEN SAID COMPONENTS.

D R A W I N G

公开(公告)号：CA935919A

公开(公告)日：1973-10-23

申请号：CA158250

申请日：1972-12-05

Applicant: IBM

Inventor： MORTON R ,  PRICER W ,  GATES H ,  HENLE R ,  NORTH W ,  CASTRUCCI P ,  MASON J

公开(公告)号：SE352781B

公开(公告)日：1973-01-08

申请号：SE1394768

申请日：1968-10-16

Applicant: IBM

Inventor： CASTRUCCI P ,  GROCHOWSKI E ,  HESS M ,  MAHERAS G ,  NORTH W

IPC: H01L21/822 ,  H01L21/331 ,  H01L21/74 ,  H01L21/8222 ,  H01L27/00 ,  H01L27/04 ,  H01L29/04 ,  H01L29/73 ,  H01L19/00

Abstract: 1,241,057. Semi-conductor devices. INTERNATIONAL BUSINESS MACHINES CORP. 2 Oct., 1968 [19 Oct., 1967], No. 46759/68. Heading H1K. A high conductivity N type zone in a device formed in a body of monocrystalline semiconductor material having a face parallel to a 100 crystallographic plane has a surface concentration of phosphorus of 2À5 to 4 x 10 3 parts per million by weight. This is achieved without significant precipitation of phosphorus due to the low dislocation density in thus aligned material. A junction isolated transistor (Fig. 2) in a typical solid circuit embodiment is formed on a 10-20 ohm. cm. P type silicon wafer 30 cut from a crystal grown along a 100 axis with its faces in a 100 plane. Subcollector region 32 is formed by diffusion and extends during epitaxial deposition of N-type epitaxial layer 34. A grid of isolation walls 37 is next diffused in prior to formation of base 38 and emitter 40 by successive diffusions. Alternatively region 32 is formed by ion implantation or etch and refill steps. Aluminium, platinum or palladium contacts 42 are formed by vapour deposition overall followed by pattern etching in a nitric-phosphoric acid mix. The diffusions are all effected through holes formed by conventional photolithographic techniques in thermal oxide layers. Arsenic is the dopant in regions 32, 34, boron in 37, 38 and phosphorus in the collector. The decline in current gain # with falling collector current is far less than in an otherwise identical device formed on a 111 orientated substrate. Manufacture of an oxide or nitride passivated planar epitaxial transistor (Fig. 1, not shown) with a phosphorus doped emitter and of an enhancement mode IGFET with N+ phosphorus doped source and drain regions is also described. The IGFET has a lower threshold voltage than its 111 orientated counterpart.

公开(公告)号：SE345930B

公开(公告)日：1972-06-12

申请号：SE454767

申请日：1967-03-31

Applicant: IBM

Inventor： AGUSTA B ,  HENLE R ,  PECORARO R ,  BARDELL P ,  CASTRUCCI P

IPC: H01L27/08 ,  G11C11/411 ,  H03K3/286 ,  H03K3/288 ,  H01L19/00

Abstract: A monolithic integrated memory arrangement comprising, in combination, a plurality of individual memory cells, functionally isolated and electrically interconnected, in which each of said memory cells is object or corresponding to another memory cell mirroring mirror image, in vertical, horizontal and diagonal direction. (Machine-translation by Google Translate, not legally binding)