公开(公告)号：GB2603403A

公开(公告)日：2022-08-03

申请号：GB202205176

申请日：2020-08-19

Applicant: IBM

Inventor： RISA MIYAZAWA ,  TAKAHITO WATANABE ,  HIROYUKI MORI ,  KEISHI OKAMOTO

IPC: H01L21/06

Abstract: A method of fabricating a connection structure is disclosed. The method includes providing a substrate that has a top surface and includes a set of pads for soldering, each of which has a pad surface exposed from the top surface of the substrate. The method also includes applying a surface treatment to a part of the top surface of the substrate close to the pads and the pad surface of each pad so as to make at least the part of the top surface and the pad surfaces of the pads rougher.

公开(公告)号：GB2603345A

公开(公告)日：2022-08-03

申请号：GB202204022

申请日：2020-08-26

Applicant: IBM

Inventor： RISA MIYAZAWA ,  TAKAHITO WATANABE ,  HIROYUKI MORI ,  KEISHI OKAMOTO

IPC: H01L23/538

Abstract: An interconnection structure is disclosed. The interconnection structure includes a base substrate, a set of conductive padsdisposed on the base substrate and an interconnection layer disposed on the base substrate. The interconnection layer has an edge located next to the set of the conductive pads and includes a set of side connection pads located and disposed at the edge of the interconnection layer. Each side connection pad is arranged with respect to a corresponding one of the conductive pads disposed on the base substrate.

公开(公告)号：GB2579325A

公开(公告)日：2020-06-17

申请号：GB202003087

申请日：2018-08-01

Applicant: IBM

Inventor： KEISHI OKAMOTO ,  AKIHIRO HORIBE ,  HIROYUKI MORI

IPC: H01L21/60 ,  H01L23/48

Abstract: A technique for interconnecting chips by using an interconnection substrate is disclosed. The interconnection substrate includes a base substrate, a first group of electrodes on the base substrate for a first chip to be mounted, and a second group of electrodes on the base substrate for a second chip to be mounted. The interconnection substrate further includes an interconnection layer that includes a first set of pads for the first chip, a second set of pads for the second chip, traces and an organic insulating material. The interconnection layer is disposed on the base substrate and located within a defined area on the base substrate between the first group of electrodes and the second group of the electrodes.