公开(公告)号：BRPI0917363B1

公开(公告)日：2020-11-17

申请号：BRPI0917363

申请日：2009-11-03

Applicant: IBM

Inventor： AKIHIRO HORIBE ,  FUMIAKI YAMADA ,  YOICHI TAIRA

IPC: G02B6/42 ,  G02B6/036

Abstract: método de alinhamento para fibra óptica de múltiplos núcleos circular relaciona-se a um método de alinhamento de fibras de múltiplos núcleos circulares, onde o método utiliza núcleos selecionados independente e individualmente para receber, transmitir, e emitir luz de dispositivos de entrada. a presente invenção relaciona-se ainda ao posicionamento das extremidades de uma fibra de múltiplos núcleos a fim de detectar e determinar as posições precisas de fibras de núcleo individualmente selecionadas.

公开(公告)号：GB2627899B

公开(公告)日：2025-02-12

申请号：GB202408555

申请日：2022-09-04

Applicant: IBM

Inventor： AKIHIRO HORIBE ,  QIANWEN CHEN ,  RISA MIYAZAWA ,  MICHAEL BELYANSKY ,  JOHN KNICKERBOCKER ,  TAKASHI HISADA

IPC: H01L21/683

Abstract: Handler wafers and methods of handling a wafer include positioning a handler, which is attached to a wafer by a bonding layer that comprises a debonding layer, an optical enhancement layer, and an anti-reflection layer. The handler is debonded from the wafer using a laser that emits laser energy at a wavelength that is absorbed by the debonding layer and that is confined to the debonding layer by the optical enhancement layer, such that the material of the debonding layer ablates when exposed to the laser energy to release the wafer.

公开(公告)号：GB2578413B

公开(公告)日：2020-08-19

申请号：GB202002809

申请日：2018-07-26

Applicant: IBM

Inventor： AKIHIRO HORIBE ,  TAKAHITO WATANABE ,  KUNIAKI SUEOKA

IPC: H01M10/0585 ,  H01M2/20 ,  H01M10/04 ,  H01M10/0562

Abstract: A technique relating to a battery structure is disclosed. A base substrate and a battery layer having a support substrate are prepared. The battery layer includes a protection layer formed on the support substrate, a film battery element formed on the protection layer and an insulator covering the film battery element. The battery layer is placed onto the base substrate with the bottom of the support substrate facing up. The support substrate is then removed from the battery layer at least in part by etching while protecting the film battery element by the protection layer. A stacked battery structure including the base substrate and the two or more battery layers is also disclosed.

公开(公告)号：GB2581684A

公开(公告)日：2020-08-26

申请号：GB202006247

申请日：2018-09-28

Applicant: IBM

Inventor： SEIJI MUNETOH ,  CHITRA SUBRAMANIAN ,  AKIHIRO HORIBE ,  KUNIAKI SUEOKA ,  YASUTERU KOHDA

IPC: H01L21/66

Abstract: A chip intermediate body includes a semiconductor region including plural chip areas. The chip areas respectively are cut out as semiconductor chips. A cut region is provided along edges of the chip areas, the cut region being cut to cut out the semiconductor chips. A contact region is provided opposite to the chip areas across the cut region, the contact region being configured to be contacted by a probe of a test unit to test the chip areas, and electric wiring is provided continuously with the cut region to connect the chip areas and the contact region.

公开(公告)号：GB2579325A

公开(公告)日：2020-06-17

申请号：GB202003087

申请日：2018-08-01

Applicant: IBM

Inventor： KEISHI OKAMOTO ,  AKIHIRO HORIBE ,  HIROYUKI MORI

IPC: H01L21/60 ,  H01L23/48

Abstract: A technique for interconnecting chips by using an interconnection substrate is disclosed. The interconnection substrate includes a base substrate, a first group of electrodes on the base substrate for a first chip to be mounted, and a second group of electrodes on the base substrate for a second chip to be mounted. The interconnection substrate further includes an interconnection layer that includes a first set of pads for the first chip, a second set of pads for the second chip, traces and an organic insulating material. The interconnection layer is disposed on the base substrate and located within a defined area on the base substrate between the first group of electrodes and the second group of the electrodes.

公开(公告)号：GB2578413A

公开(公告)日：2020-05-06

申请号：GB202002809

申请日：2018-07-26

Applicant: IBM

Inventor： AKIHIRO HORIBE ,  TAKAHITO WATANABE ,  KUNIAKI SUEOKA

IPC: H01M10/0585 ,  H01M2/20 ,  H01M10/04 ,  H01M10/0562

Abstract: A technique relating to a battery structure is disclosed. A base substrate and a battery layer having a support substrate are prepared. The battery layer includes a protection layer formed on the support substrate, a film battery element formed on the protection layer and an insulator covering the film battery element. The battery layer is placed onto the base substrate with the bottom of the support substrate facing up. The support substrate is then removed from the battery layer at least in part by etching while protecting the film battery element by the protection layer. A stacked battery structure including the base substrate and the two or more battery layers is also disclosed.