公开(公告)号：DE2429556A1

公开(公告)日：1975-01-16

申请号：DE2429556

申请日：1974-06-20

Applicant: IBM

Inventor： HO ALLEN PANG-I ,  LEE HUA-TUNG ,  TING YEE-MING

IPC: G06T7/00 ,  G06K9/00 ,  G06K9/46 ,  G07C9/00 ,  A61B5/10 ,  G06K9/16

Abstract: 1428636 Pattern recognition systems INTERNATIONAL BUSINESS MACHINES CORP 2 May 1974 [29 June 1973 (2)] 19275/74 Heading G4R An arrangement for recognizing the merger of two lines in a pattern, e.g. a printed circuit or a minutia consisting of two merging ridge lines or of a ridge end defined by two merging interridge spaces in a fingerprint, includes a logic matrix comprising an array of cells which are operative to form conductive paths from the centre of the matrix to its periphery, the disposition of the paths corresponding to the' disposition of the lines in the pattern. Outputs from the peripheral cells are used to identify the presence of a merger. The output of a scanner viewing the pattern is digitized and passed to shift register stores which deliver, in true and inverse form, signals representative of the portion of the pattern appearing in a notional 12 x 12 bit window moving over the pattern. The true signals pass to a logic matrix comprising a 12 Î 12 array of cells as indicated in Fig. 2. Each cell is such that it provides an output to its neighbours if it receives an input from a neighbour and from a pattern part. Fig. 2 shows by the black dots those cells which provide an output when a minutia consisting of merging ridges is present in the window. The operated cells form continuous paths from the 4 central cells, connected to voltage source V, to certain peripheral cells. The inverse signals pass to a second logic matrix which performs a similar function, Fig. 3. The outputs from the 44 peripheral cells of the first matrix pass to a circuit (Fig. 6, not shown) which determines whether there are three separate groups of 1-bits and which, if this is so, gives an output indicating the presence of a 3-armed minutia. The output is inhibited if the number of 1-bits in any group exceeds, for example 5 so that a minutia not yet clearly positioned in the window is not recognized and so that excessively wide arms are rejected. The 44 outputs of the second matrix are used in a similar manner to recognize the presence of the split between the ridges. If both a split and a 3-armed minutia are recognized a signal indicating that a minutia is present in the window is generated, and may be used to store the coordinates of the minutia. In order to prevent recognition of a minutia more than once as it passes through the window the outputs of a symmetrically-placed cruciform array (Fig. 11, not shown) of 28 of the cells of the second matrix, together with a signal indicative of the quadrant in which the split lies, are passed to a circuit (Fig. 10, not shown) which prevents read-out of the co-ordinates except when the minutia is first recognized.

公开(公告)号：DE3165481D1

公开(公告)日：1984-09-20

申请号：DE3165481

申请日：1981-02-25

Applicant: IBM

Inventor： HO ALLEN PANG-I ,  HORNG CHENG TZONG

IPC: H01L29/73 ,  H01L21/033 ,  H01L21/331 ,  H01L29/417 ,  H01L29/732 ,  H01L21/00 ,  H01L21/285 ,  H01L21/60 ,  H01L21/76 ,  H01L29/72

公开(公告)号：DE3279966D1

公开(公告)日：1989-11-02

申请号：DE3279966

申请日：1982-12-07

Applicant: IBM

Inventor： CHU SHAO-FU ,  HO ALLEN PANG-I ,  HORNG CHENG TZONG ,  KEMLAGE BERNARD MICHAEL

IPC: H01L21/76 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762

Abstract: A method of forming a wide deep dielectric filled isolation trench in the surface of a silicon semiconductor substrate by forming a wide plug of chemical vapor deposited silicon dioxide in the trench, filling the remaining unfilled trench portions by chemical vapor depositing a layer of silicon dioxide over the substrate and etching back this layer. The method produces chemically pure, planar wide deep dielectric filled isolation trenches and may also be used to simultaneously produce narrow deep dielectric filled isolation trenches.