中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

12 records (took 0.019 seconds)

    FABRICATION PROCESS FOR A SHALLOW EMITTER, NARROW INTRINSIC BASE TRANSISTOR
    2.
    发明专利
    FABRICATION PROCESS FOR A SHALLOW EMITTER, NARROW INTRINSIC BASE TRANSISTOR 未知

    公开(公告)号：DE3380889D1

    公开(公告)日：1989-12-28

    申请号：DE3380889

    申请日：1983-03-10

    Applicant: IBM

    Inventor： KEMLAGE BERNARD MICHAEL

    IPC: H01L29/73 ,  H01L21/033 ,  H01L21/225 ,  H01L21/331 ,  H01L29/10 ,  H01L29/732 ,  H01L29/08 ,  H01L29/72

    Abstract: A high performance bipolar transistor having a shallow emitter and a narrow intrinsic base region is fabricated by a minimum number of process steps. A silicon semiconductor body 10 is provided with regions of monocrystalline silicon isolated from one another by isolation regions (18) an epitaxial layer (14) and a buried subcollector (12). A layer (24) of polycrystalline silicon is deposited on the body. The surface of the polycrystalline silicon layer (24) is oxidized and the polycrystalline silicon is implanted with a base impurity. Silicon nitride and oxide layers (28, 30) are deposited on the polysilicon layer. An opening is made in the surface oxide layer (28) and the silicon nitride layer (30) to define the emitter area of the transistor. The polycrystalline silicon is thermally oxidized to drive the base impurity into the substrate. The thermal oxide is removed in an isotropic etch to leave an oxide sidewall cover (38) on the polycrystalline silicon. An emitter impurity is ion implanted into the polycrystalline silicon in the emitter area and then driven into the substrate. Collector, base and emitter contact openings are made and conductive metallurgy is formed.

    4.
    发明专利
    未知

    公开(公告)号：DE3381605D1

    公开(公告)日：1990-06-28

    申请号：DE3381605

    申请日：1983-02-23

    Applicant: IBM

    Inventor： BARSON FRED ,  KEMLAGE BERNARD MICHAEL

    IPC: H01L29/73 ,  H01L21/225 ,  H01L21/3215 ,  H01L21/331 ,  H01L29/10 ,  H01L21/285 ,  H01L21/82

    Abstract: A method for fabricating high performance NPN bipolar transistors which result in shallow, narrow base devices is described.The method includes depositing a polycrystalline silicon layer (30) over a monocrystalline silicon surface in which the base and emitter regions (42, 44) of the transistor are to be formed. Boron ions (32) are ion implanted into the polycrystalline silicon layer (30) near the interface of the polycrystalline silicon layer with the monocrystalline silicon layer. An annealing of the layer structure partially drives in the boron into the monocrystalline silicon substrate. Arsenic ions (38) are ion implanted into the polycrystalline silicon layer (30). A second annealing step is utilized to fully drive in the boron to form the base region (42) and simultaneously therewith drive in the arsenic to form the emitter region (44) of the transistor. This process involving a two-step annealing process for the boron implanting ions is necessary to create a base with sufficient width and doping to avoid punch-through. There is also described a method for forming NPN transistors in an integrated circuit.

    INTEGRATED CIRCUIT STRUCTURE AND METHOD FOR FORMING A RECESSED ISOLATION STRUCTURE FOR INTEGRATED CIRCUITS
    6.
    发明专利
    INTEGRATED CIRCUIT STRUCTURE AND METHOD FOR FORMING A RECESSED ISOLATION STRUCTURE FOR INTEGRATED CIRCUITS 未知

    公开(公告)号：DE3279525D1

    公开(公告)日：1989-04-13

    申请号：DE3279525

    申请日：1982-08-10

    Applicant: IBM

    Inventor： JOY RICHARD CARLETON ,  KEMLAGE BERNARD MICHAEL ,  MAUER IV JOHN LESTER

    IPC: H01L21/76 ,  H01L21/31 ,  H01L21/331 ,  H01L21/74 ,  H01L21/762 ,  H01L21/763 ,  H01L21/822 ,  H01L27/04 ,  H01L29/73

    Abstract: An integrated circuit structure having substrate contacts formed as a part of the isolation structure and method for making the same is described. The integrated circuit structure is composed of a monocrystalline silicon body (2, 4) having a pattern of dielectric isolation surrounding regions of the monocrystalline silicon in the body. The dielectric isolation pattern includes a recessed dielectric portion (22, 24) at and just below the surface of the integrated circuit and a deep portion which extends from the side of the recessed dielectric portion opposite to that portion at the surface of said body into the monocrystalline silicon body. A highly doped polycrystalline silicon substrate contact (20) is located within the deep portion of the pattern of isolation. At certain locations the deep portion of the pattern extends to the surface of the silicon body where interconnection metallurgy can electrically contact the polycrystalline silicon so as to form a substrate contact to the bottom of the deep portion of the isolation where the contact electrically connects to the silicon body. Any of a variety of integrated circuit device structures may be incorporated within the monocrystalline silicon regions. These devices include bipolar transistors, field effect transistors, capacitors, diodes, resistors and the like.

    INTEGRATED CIRCUIT STRUCTURE AND METHOD FOR FORMING A RECESSED ISOLATION STRUCTURE FOR INTEGRATED CIRCUITS
    7.
    发明专利
    INTEGRATED CIRCUIT STRUCTURE AND METHOD FOR FORMING A RECESSED ISOLATION STRUCTURE FOR INTEGRATED CIRCUITS 未知

    公开(公告)号：DE3279524D1

    公开(公告)日：1989-04-13

    申请号：DE3279524

    申请日：1982-08-10

    Applicant: IBM

    Inventor： JOY RICHARD CARLETON ,  KEMLAGE BERNARD MICHAEL ,  MAUER IV JOHN LESTER

    IPC: H01L21/822 ,  H01L21/302 ,  H01L21/31 ,  H01L21/3205 ,  H01L21/331 ,  H01L21/74 ,  H01L21/76 ,  H01L21/762 ,  H01L21/763 ,  H01L23/52 ,  H01L27/04 ,  H01L29/73

    Abstract: An integrated circuit structure having substrate contacts formed as a part of the isolation structure and the method to form such structure is described. The integrated circuit structure is composed of a monocrystalline silicon body (2, 4) having a pattern of dielectric isolation surrounding regions of the monocrystalline silicon in the body. The dielectric isolation pattern includes a recessed dielectric portion (14) at and just below the surface of the integrated circuit and a deep portion (30) which extends through the recessed dielectric portion (14) and extends further into the monocrystalline silicon body (2, 4) than the recessed portion. A highly doped polycrystalline silicon substrate contact (30) is located within the deep portion of the pattern of isolation. The substrate contact extends from the surface of the pattern of isolation down to the bottom of the deep portion of the isolation where the contact electrically connects to the silicon body. Any of a variety of integrated circuit device structures may be incorporated within the monocrystalline silicon regions. These devices include bipolar transistors, field effect transistors, capacitors, diodes, resistors and the like.

    9.
    发明专利
    未知

    公开(公告)号：IT1150033B

    公开(公告)日：1986-12-10

    申请号：IT2368980

    申请日：1980-07-25

    Applicant: IBM

    Inventor： KEMLAGE BERNARD MICHAEL

    IPC: C23C16/40 ,  H01L21/316 ,  H01L

    Abstract: A method is described for forming a silicon dioxide layer on a semiconductor substrate in a furnace heated reaction zone of a chemical vapor deposition reactor having an input end for gaseous reactants wherein the silicon dioxide layer is not subject to degradation during subsequent oxidation cycles. A gaseous chlorosilane is mixed with nitrous oxide gas in the reactor. Oxygen gas is added, between about 0.25% to 10% by volume of total reactive gas mixture, to the chlorosilane and nitrous oxide gases in the reaction zone where the temperature is between about 800 DEG C. to 1200 DEG C. in a pressure of less than about 5 torr to deposit the silicon dioxide layer onto the substrate.

Patent Agency Ranking