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公开(公告)号：JPH10178028A
公开(公告)日：1998-06-30
申请号：JP31842097
申请日：1997-11-19
Applicant: IBM
Inventor： HOFFMEYER MARK KENNETH
IPC: H01L23/40 , H01L21/52 , H01L21/58 , H01L21/60 , H01L23/367 , H01L23/373
Abstract: PROBLEM TO BE SOLVED: To provide a mounting technique which facilitates removal and exchange when requiring reprocess. SOLUTION: A laminated heat sink contains a metal heat sink 22, and the heat sink 22 is adhered to a foil layer 24. A chip 10 is fitted on the foil layer 24 in a cutout opening 32 in a carrier 12. When having to remove and exchange the chip 10, the foil layer 24 is separated from the heat sink 22, so that the foil layer 24, the chip 10 and chip fitting adhesives 30 are integrally removed, and the chip 10 can be simply detached and exchanged.
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公开(公告)号：JP2004304172A
公开(公告)日：2004-10-28
申请号：JP2004073554
申请日：2004-03-15
Applicant: Internatl Business Mach Corp
, インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation Inventor： BRODSKY WILLIAM LOUIS , HOFFMEYER MARK KENNETH , STACK JAMES R
CPC classification number: H05K1/0271 , H05K1/0224 , H05K1/0253 , H05K1/112 , H05K2201/0191 , H05K2201/093 , H05K2201/09609 , H05K2201/09681 , H05K2201/09718 , H05K2201/10719 , Y10T29/49155 , Y10T29/49156
Abstract: PROBLEM TO BE SOLVED: To provide a method and a structure for reinforcing interconnection performance between a land grid array (LGA) module and an electrical connector such as a printed wiring board. SOLUTION: A multilayer printed wiring board comprises a plurality of preformed ground layers and power supply layers. At least one of the preformed ground layers and power supply layers comprises a structure for reducing a thickness change to a minimum in order to reduce changes in the thickness to a minimum. The structure for reducing the thickness change to a minimum comprises an aperture pattern in the selected area of at least one layer of the preformed ground layers and power supply layers. The selected area is located near a preformed module site such as an LGA module site in the ground layers and the power supply layers. The selected area may include a region surrounding each preformed module site and also can also include one region in the module site. COPYRIGHT: (C)2005,JPO&NCIPI
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公开(公告)号：MY126300A
公开(公告)日：2006-09-29
申请号：MYPI9705346
申请日：1997-11-11
Applicant: IBM
Inventor： HOFFMEYER MARK KENNETH
IPC: H01L23/40 , H05K3/34 , H01L21/52 , H01L21/58 , H01L21/60 , H01L23/367 , H01L23/373 , H01L31/18
Abstract: A DIRECT CHIP ATTACH TO HEATSINK STRUCTURE IS SHOWN AND DESCRIBED WHICH IMPLEMENTS REWORK WHEN THE CHIP (10, 56, 72) MUST BE REMOVED AND REPLACED. A LAMINATED HEATSINK (20) INCLUDES A METAL HEATSINK (22, 51, 70) WITH A FOIL LAYER (24, 36, 57, 87) ADHERED TO THE CHIP ATTACHMENT SURFACE WITH THE ASSEMBLY SECURED TO A CARRIER (12, 52, 76) AT A CUTOUT OPENING (32) THEREIN THAT DEFINES THE CHIP ATTACH SITE.THE ADHESIVE (26, 28, 38, 59, 88, 89), EITHER A DRY FILM ADHESIVE OR A PRESSURE SENSITIVE ADHESIVE, SECURES FOIL LAYER TO HEATSINK AND PROVIDES THE INTERFACE OF SEPARATION WHEN A CHIP MUST BE REMOVED AND REPLACED.BY PEELING THE FOIL AWAY FROM THE HEATSINK, THE FOIL, CHIP AND NON-REWORKABLE DIE ATTACH ADHESIVE (30) ARE REMOVED AS A UNIT, LEAVING NO CHIP ATTACH ADHESIVE RESIDUE AT THE ATTACHMENT SITE TO BE SCRAPED OR ABRADED AWAY. THE REPLACEMENT CHIP CAN BE INSTALLED EITHER BY DIRECTLY INSTALLING WITH NEW DIE ATTACH ADHESIVE OR BY FIRST RESTORING THE FOIL LAYER PRIOR TO CHIP INSTALLATION. THE FOIL MAY BE APPLIED OVER THE ENTIRE SURFACE OF THE HEATSINK OR MAY BE PATTERNED TO PROVIDE THE LAMINATED FOIL COATING ONLY BENEATH THE CHIP ATTACH SITE. FURTHER, THE FOIL AND HEATSINK MAY BE OF DISSIMILAR METALS TO IMPART VARYING CHARACTERISTICS, SUCH AS A SOLDERABLE SURFACE TO AN ALUMINUM HEATSINK. ALSO, THE TECHNIQUE WOULD BE APPLICABLE TO DIRECT CHIP ATTACHMENT DIRECTLY TO A RIGID OR FLEXIBLE ELECTRONIC CIRCUIT CARRIER ASSEMBLY.IN ANOTHER FORM, THE INVENTION MAY BE IMPLEMENTED USING A FOIL LAYER WITH ADHESIVE ON BOTH SIDES TO SECURE THE CHIP TO A HEATSINK AT THE CARRIER ASSEMBLY CHIP ATTACH LOCATION. A FURTHER FORM OF THE INVENTION USES A TAPE CAVITY PACKAGING STRUCTURE WHEREIN THE CARRIER ASSEMBLY INCLUDES A LAMINATED CARRIER/HEATSINK WITH ALIGNED OPENINGS THAT CREATE A CHIP ATTACH CAVITY IN THE PACKAGE AND FOIL BONDED TO THE HEATSINK ACROSS THE BASE OF THE CHIP CAVITY BY A LAYER OF ADHESIVE THAT ALSO PRESENTS A CHIP ATTACH ADHESIVE ACROSS THE BASE OF THE CHIP ATTACH CAVITY. THE STRUCTURE AFFORDS A LOW PROFILE ASSEMBLY, ENABLES REWORK/REPLACEMENT, SHORTENS WIRE LENGTHS AND REDUCES WIREBOND LOOP HEIGHTS.(FIG.1)
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Patent Agency Ranking
公开(公告)号：DE69834768D1
公开(公告)日：2006-07-20
申请号：DE69834768
申请日：1998-04-29
Applicant: IBM
Inventor： GOODMAN DALE ERNEST , HOFFMEYER MARK KENNETH , KRABBENHOFT ROGER SCOTT
Abstract: A printed circuit connector terminal pad coating technique is disclosed which functions as a single universal pad surface which supports multiple electrical connection practices including wirebonding, soldering, and wear resistant, pad on pad mechanical connection. The tri-plate surface treatment includes an initial diffusion resistant coating of nickel; an intermediate layer of hard, wear resistant noble or semi-noble metal that provides pad on pad connector reliability and affords a metallurgically stable solder joints and wirebond interfaces; and a final coating of soft gold. The intermediate layer may be pure palladium having a nominal thickness of 35 microinches or a layer of gold, hardened by cobalt, nickel, iron or a combination of these dopants to effect a hardness of 200 to 250 (Knoop scale) . The use of a common surface treatment for the multiple attachment processes is implemented with a single masking step, rather than a sequence of selective masking, plating and stripping operations. In the printed circuit environment, the masking is provided by the final covering that encloses, seals, and electrically insulates the conductors in a circuit board application or in the instance of a flexcable, the adhesive coated flexible coverlay the covers and seals the copper conductor elements while exposing the conductor terminal pads.
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公开(公告)号：DE69834768T2
公开(公告)日：2007-05-24
申请号：DE69834768
申请日：1998-04-29
Applicant: IBM
Inventor： GOODMAN DALE ERNEST , HOFFMEYER MARK KENNETH , KRABBENHOFT ROGER SCOTT
Abstract: A printed circuit connector terminal pad coating technique is disclosed which functions as a single universal pad surface which supports multiple electrical connection practices including wirebonding, soldering, and wear resistant, pad on pad mechanical connection. The tri-plate surface treatment includes an initial diffusion resistant coating of nickel; an intermediate layer of hard, wear resistant noble or semi-noble metal that provides pad on pad connector reliability and affords a metallurgically stable solder joints and wirebond interfaces; and a final coating of soft gold. The intermediate layer may be pure palladium having a nominal thickness of 35 microinches or a layer of gold, hardened by cobalt, nickel, iron or a combination of these dopants to effect a hardness of 200 to 250 (Knoop scale) . The use of a common surface treatment for the multiple attachment processes is implemented with a single masking step, rather than a sequence of selective masking, plating and stripping operations. In the printed circuit environment, the masking is provided by the final covering that encloses, seals, and electrically insulates the conductors in a circuit board application or in the instance of a flexcable, the adhesive coated flexible coverlay the covers and seals the copper conductor elements while exposing the conductor terminal pads.
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公开(公告)号：MY115395A
公开(公告)日：2003-05-31
申请号：MYPI9802088
申请日：1998-05-08
Applicant: IBM
Inventor： GOODMAN DALE ERNEST , HOFFMEYER MARK KENNETH , KRABBENHOFT ROGER SCOTT
Abstract: A PRINTED CIRCUIT CONNECTOR TERMINAL PAD COATING TECHNIQUE IS DISLCOSED WHICH FUNCTIONS AS A SINGLE UNIVERSAL PAD SURFACE WHICH SUPPORTS MULTIPLE ELECTRICAL CONNECTION PRACTICES INCLUDING WIREBONDING, SOLDERING, AND WEAR RESISTANT, PAD ON PAD MECHANICAL CONNECTION. THE TRI-PLATE SURFACE TREATMENT INCLUDES AN INITIAL DIFFUSION RESISTANT COATING (37) OF NICKEL; AN INTERMEDIATE LAYER (39) OF HARD, WEAR RESISTANT NOBLE OR SEMI-NOBLE METAL THAT PROVIDES PAD ON PAD CONNECTOR RELIABILITY AND AFFORDS A METALLURGICALLY STABLE SOLDER JOINTS AND WIREBOND INTERFACES; AND A FINAL COATING (41) OF SOFT GOLD. THE INTERMEDIATE LAYER (39) MAY BE PURE PALLADIUM HAVING A NOMINAL THICKNESS OF (35 MICROINCHES) OR A LAYER OF GOLD, HARDENED BY COBALT, NICKEL, IRON OR A COMBINATION OF THESE DOPANTS TO EFFECT A HARDNESS OF 200 TO 250 (KNOOP SCALE). THE USE OF A COMMON SURFACE TREATMENT FOR THE MULTIPLE ATTACHMENT PRICESSES IS IMPLEMENTED WITH A SINGLE MASKING STEP, RATHER THAN A SEQUENCE OF SELECTIVE MASKING, PLATING AND STRIPPING OPERATIONS. IN THE PRINTER CIRCUIT ENVIRONMENT, THE MASKING IS PROVIDED BY THE FINAL COVERING THAT ENCLOSES, SEALS, AND ELECTRICALLY INSULATES THE CONDUCTORS IN A CIRCUIT BOARD APPLICATION OR IN THE INSTANCE OF A FLEXCABLE, THE ADHESIVE COATED FLEXIBLE COVERLAY (34) THE COVERS AND SEALS THE COPPER CONDUCTOR ELEMENTS WHILE EXPOSING THE CONDUCTOR TERMINAL PADS (33).
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公开(公告)号：SG71123A1
公开(公告)日：2000-03-21
申请号：SG1998001312
申请日：1998-06-08
Applicant: IBM
Inventor： GOODMAN DALE ERNEST , HOFFMEYER MARK KENNETH , KRABBENHOFT ROGER SCOTT
Abstract: A printed circuit connector terminal pad coating technique is disclosed which functions as a single universal pad surface which supports multiple electrical connection practices including wirebonding, soldering, and wear resistant, pad on pad mechanical connection. The tri-plate surface treatment includes an initial diffusion resistant coating of nickel; an intermediate layer of hard, wear resistant noble or semi-noble metal that provides pad on pad connector reliability and affords a metallurgically stable solder joints and wirebond interfaces; and a final coating of soft gold. The intermediate layer may be pure palladium having a nominal thickness of 35 microinches or a layer of gold, hardened by cobalt, nickel, iron or a combination of these dopants to effect a hardness of 200 to 250 (Knoop scale) . The use of a common surface treatment for the multiple attachment processes is implemented with a single masking step, rather than a sequence of selective masking, plating and stripping operations. In the printed circuit environment, the masking is provided by the final covering that encloses, seals, and electrically insulates the conductors in a circuit board application or in the instance of a flexcable, the adhesive coated flexible coverlay the covers and seals the copper conductor elements while exposing the conductor terminal pads.
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公开(公告)号：SG60149A1
公开(公告)日：1999-02-22
申请号：SG1997004027
申请日：1997-11-12
Applicant: IBM
Inventor： HOFFMEYER MARK KENNETH
IPC: H01L23/40 , H01L21/52 , H01L21/58 , H01L21/60 , H01L23/367 , H01L23/373 , H01L21/36
Abstract: A direct chip attach to heatsink structure is shown and described which implements rework when the chip must be removed and replaced. A laminated heatsink includes a metal heatsink with a foil layer adhered to the chip attachment surface with the assembly secured to a carrier at a cutout opening therein that defines the chip attach site. The adhesive, either a dry film adhesive or a pressure sensitive adhesive, secures foil layer to heatsink and provides the interface of separation when a chip must be removed and replaced. By peeling the foil away from the heatsink, the foil, chip and non-reworkable die attach adhesive are removed as a unit, leaving no chip attach adhesive residue at the attachment site to be scraped or abraded away. The replacement chip can be installed either by directly installing with new die attach adhesive or by first restoring the foil layer prior to chip installation. The foil may be applied over the entire surface of the heatsink or may be patterned to provide the laminated foil coating only beneath the chip attach site. Further, the foil and heatsink may be of dissimilar metals to impart varying characteristics, such as a solderable surface to an aluminum heatsink. Also, the technique would be applicable to direct chip attachment directly to a rigid or flexible electronic circuit carrier assembly. In another form, the invention may be implemented using a foil layer with adhesive on both sides to secure the chip to a heatsink at the carrier assembly chip attach location. A further form of the invention uses a tape cavity packaging structure wherein the carrier assembly includes a laminated carrier/heatsink with aligned openings that create a chip attach cavity in the package and foil bonded to the heatsink across the base of the chip cavity by a layer of adhesive that also presents a chip attach adhesive across the base of the chip attach cavity. The structure affords a low profile assembly, enables rework/replacement, shortens wire lengths and reduces wirebond loop heights.
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