公开(公告)号：EP2108192A4

公开(公告)日：2009-12-30

申请号：EP07855285

申请日：2007-12-20

Applicant: IBM

Inventor： LIU YAOCHANG ,  CHIDAMBARRAO DURESETI ,  RIM KERN ,  GLUSCHENKOV OLEG ,  MO RENEE T ,  HOLT JUDSON R

IPC: H01L27/10 ,  H01L21/336 ,  H01L21/82 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L21/823864 ,  H01L21/76886 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/3279 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

公开(公告)号：EP2050128A4

公开(公告)日：2009-12-23

申请号：EP07813250

申请日：2007-07-24

Applicant: IBM

Inventor： CHAKRAVARTI ASHIMA B ,  CHIDAMBARRAO DURESETI ,  HOLT JUDSON R ,  LIU YAOCHENG ,  RIM KERN

IPC: H01L21/336 ,  H01L21/762 ,  H01L21/8238

CPC classification number: H01L21/823864 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/7843 ,  H01L29/7848

公开(公告)号：JP2007329474A

公开(公告)日：2007-12-20

申请号：JP2007135089

申请日：2007-05-22

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DYER THOMAS W ,  FANG SUNFEI ,  HOLT JUDSON R

IPC: H01L21/8238 ,  H01L21/20 ,  H01L21/336 ,  H01L21/8244 ,  H01L27/092 ,  H01L27/11 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/045 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823857 ,  H01L29/1037 ,  H01L29/78 ,  H01L29/7853

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor substrate having different surface orientations (namely, hybrid surface orientation).
SOLUTION: In the semiconductor substrate, a first device area 2 has a substantially flat surface 16A which is oriented to one orientation of group of first equivalent crystal surfaces, and a second device area contains a protrusive semiconductor structure 18 having a plurality of cross surfaces 16B which are oriented to an orientation of group of other equivalent crystal surfaces. A semiconductor device structure can be formed using such a semiconductor substrate. Particularly, a first field-effect transistor (FET) can be formed in the first device area, the first FET contains a channel which is located along a substantially flat surface in the first device area. A second complementary FET can be formed in the second device area, and the second complementary FET contains a channel which is located along the plurality of cross surfaces of the protrusive semiconductor structure in the second device area.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供具有不同表面取向（即混合表面取向）的半导体衬底。 解决方案：在半导体衬底中，第一器件区域2具有基本上平坦的表面16A，其被定向为第一等效晶体表面的一组取向，并且第二器件区域包含突出半导体结构18，突出半导体结构18具有多个 横向表面16B被定向成其他等效晶体表面的组的取向。 可以使用这种半导体衬底形成半导体器件结构。 特别地，第一场效应晶体管（FET）可以形成在第一器件区域中，第一FET包含沿着第一器件区域中的基本上平坦的表面定位的沟道。 第二互补FET可以形成在第二器件区域中，并且第二互补FET包含沿着第二器件区域中的突出半导体结构的多个十字表面定位的沟道。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：WO2011133339A3

公开(公告)日：2012-03-08

申请号：PCT/US2011031693

申请日：2011-04-08

Applicant: IBM ,  CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON R ,  LI JINGHONG ,  NEWBURY JOSEPH S ,  ONTALUS VIOREL ,  PARK DAE-GYU ,  ZHU ZHENGMAO

Inventor： CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON R ,  LI JINGHONG ,  NEWBURY JOSEPH S ,  ONTALUS VIOREL ,  PARK DAE-GYU ,  ZHU ZHENGMAO

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8228 ,  H01L27/092

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834

Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include an FET gate stack 18 located on an upper surface of a semiconductor substrate 12. The FET gate stack includes source and drain extension regions 28 located within the semiconductor substrate at a footprint of the FET gate stack. A device channel 40 is also present between the source and drain extension regions and beneath the gate stack. The structure further includes embedded stressor elements 34 located on opposite sides of the FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes a lower layer of a first epitaxy 36 doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy 38 doped semiconductor material located atop the lower layer. The lower layer of the first epitaxy doped semiconductor material has a lower content of dopant as compared to the upper layer of the second epitaxy doped semiconductor material. The structure further includes a monolayer of dopant located within the upper layer of each of the embedded stressor elements. The monolayer of dopant is in direct contact with an edge of either the source extension region or the drain extension region.

Abstract translation: 公开了在其中具有嵌入的应力元件的半导体结构。 所公开的结构包括位于半导体衬底12的上表面上的FET栅极堆叠18. FET栅极堆叠包括在FET栅极堆叠的覆盖区处位于半导体衬底内的源极和漏极延伸区域28。 器件沟道40也存在于源极延伸区域和漏极延伸区域之间以及栅极堆叠层下方。 该结构还包括位于FET栅极堆叠的相对侧并且位于半导体衬底内的嵌入式应力元件34。 每个嵌入的应力元件包括第一外延36掺杂半导体材料的下层，其具有不同于半导体衬底的晶格常数的晶格常数并且在器件沟道中施加应变，并且第二外延的上层 38掺杂的半导体材料位于下层的顶部。 与第二外延掺杂半导体材料的上层相比，第一外延掺杂半导体材料的下层具有较低的掺杂剂含量。 该结构还包括位于每个嵌入的应力元件的上层内的掺杂剂单层。 掺杂剂的单层与源极延伸区域或漏极延伸区域的边缘直接接触。

公开(公告)号：WO2008085686A2

公开(公告)日：2008-07-17

申请号：PCT/US2007088266

申请日：2007-12-20

Applicant: IBM ,  LIU YAOCHANG ,  CHIDAMBARRAO DURESETI ,  RIM KERN ,  GLUSCHENKOV OLEG ,  MO RENEE T ,  HOLT JUDSON R

Inventor： LIU YAOCHANG ,  CHIDAMBARRAO DURESETI ,  RIM KERN ,  GLUSCHENKOV OLEG ,  MO RENEE T ,  HOLT JUDSON R

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/823864 ,  H01L21/76886 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/3279 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed suicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed suicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.

Abstract translation: 虽然嵌入式硅锗合金和硅碳合金提供了许多有用的应用，特别是通过应力工程增强MOSFET的迁移率，在这些表面上形成合金化硅化物降低了器件性能。 本发明提供了在放置在半导体衬底上的硅合金表面上提供非合金硅化物的结构和方法。 这使得能够在具有嵌入式SiGe的迁移率增强的PFET和在同一半导体衬底上具有嵌入的Si：C的迁移率增强的NFET形成低电阻触点。 此外，本发明提供了在栅极电介质的电平之上的厚外延硅合金，特别是厚的外延Si：C合金的方法，以增加晶体管器件上的沟道上的应力。

公开(公告)号：JP2008131033A

公开(公告)日：2008-06-05

申请号：JP2007270238

申请日：2007-10-17

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： UTOMO HENRY K ,  HOLT JUDSON R ,  HAINING S YANG

IPC: H01L21/8238 ,  H01L21/76 ,  H01L21/762 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1203 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045 ,  H01L29/78687

Abstract: PROBLEM TO BE SOLVED: To provide a device and a method for improving positive hole mobility.
SOLUTION: A semiconductor device includes an oxide layer on a first silicon layer and a second silicon layer on the oxide layer, and the oxide layer is formed between the first silicon layer and the second silicon layer. A first silicon layer 210 and a second silicon layer 230 include the same crystal orientations. The device further includes a tapered germanium layer 250 on the first silicon layer, and the tapered germanium layer is in contact with a spacer 240 and the first silicon layer, but not in contact with an oxide layer 220. A lower part of the tapered germanium layer contains a higher concentration of germanium than that of an upper part of the tapered germanium layer, and there exists no germanium at the upper face of the tapered germanium layer.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种改善空穴迁移率的装置和方法。 解决方案：半导体器件包括在第一硅层上的氧化物层和氧化物层上的第二硅层，并且氧化物层形成在第一硅层和第二硅层之间。 第一硅层210和第二硅层230包括相同的晶体取向。 该器件还包括在第一硅层上的锥形锗层250，并且锥形锗层与间隔物240和第一硅层接触，但不与氧化物层220接触。锥形锗的下部 层包含比锥形锗层的上部更高的锗浓度，并且在锥形锗层的上表面上不存在锗。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2006049897A

公开(公告)日：2006-02-16

申请号：JP2005219835

申请日：2005-07-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DAINE C BOYD ,  HOLT JUDSON R ,  LEONG MEIKEI ,  MO RENEE T ,  REN ZHIBIN ,  SHAHIDI GHAVAM G

IPC: H01L29/786 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092

CPC classification number: H01L27/1203 ,  H01L21/76283 ,  H01L21/823892 ,  H01L21/84 ,  H01L29/66772 ,  H01L29/78609 ,  H01L29/78618 ,  H01L29/78696

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a super-steep retrograde well field effect transistor device, and to provide an ultra-thin body FET device manufactured by the same.
SOLUTION: The method for manufacturing a super-steep retrograde well field effect transistor device starts with an SOI layer formed on a substrate, for example, an embedded oxide layer. The SOI layer is thinned so as to form an ultra-thin SOI layer. A separation trench is formed for dividing the SOI layer into an N ground layer region and a P ground layer region. The N and P ground layer regions formed in the SOI layer are doped with N-type and P-type dopants to a high concentration level. A semiconductor channel region is formed on the N and P ground layer regions. The source region and the drain region of the FET and the gate electrode stack on the channel region are formed. As desired, a diffusion retarding layer is formed between the SOI ground layer regions and the channel regions.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于制造超陡逆向井场效应晶体管器件的方法，并提供由其制造的超薄体FET器件。 解决方案：用于制造超陡逆向井场效应晶体管器件的方法从形成在衬底上的SOI层，例如嵌入的氧化物层开始。 SOI层被薄化以形成超薄SOI层。 形成分离沟槽，用于将SOI层分成N个接地层区域和P个接地层区域。 形成在SOI层中的N和P接地层区域以高浓度水平掺杂有N型和P型掺杂剂。 在N和P接地层区域上形成半导体沟道区。 形成FET的源极区域和漏极区域以及沟道区域上的栅电极堆叠。 根据需要，在SOI接地层区域和沟道区域之间形成扩散延迟层。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：WO2011162977A3

公开(公告)日：2012-03-15

申请号：PCT/US2011039892

申请日：2011-06-10

Applicant: IBM ,  CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON R ,  JOHNSON JEFFREY B ,  LI JINGHONG ,  PARK DAE-GYU ,  ZHU ZHENGMAO

Inventor： CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON R ,  JOHNSON JEFFREY B ,  LI JINGHONG ,  PARK DAE-GYU ,  ZHU ZHENGMAO

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7834 ,  H01L29/7848

Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack (18) located on an upper surface of a semiconductor substrate (12). The at least one FET gate stack includes source and drain extension regions (28) located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel (40) is also present between the source and drain extension regions (28) and beneath the at least one gate stack (18). The structure further includes embedded stressor elements (33) located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes, from bottom to top, a first layer of a first epitaxy doped semiconductor material (35) having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, a second layer of a second epitaxy doped semiconductor material (36) located atop the first layer, and a delta monolayer of dopant located on an upper surface of the second layer. The structure further includes a metal semiconductor alloy contact (45) located directly on an upper surface of the delta monolayer (37).

Abstract translation: 公开了在其中具有嵌入的应力元件的半导体结构。 所公开的结构包括位于半导体衬底（12）的上表面上的至少一个FET栅叠层（18）。 所述至少一个FET栅极堆叠包括位于所述至少一个FET栅极堆叠中的覆盖区内的所述半导体衬底内的源极和漏极延伸区域（28）。 器件通道（40）也存在于源极和漏极延伸区域（28）之间并且在至少一个栅极堆叠（18）下方。 该结构还包括位于至少一个FET栅极堆叠的相对侧上并且在半导体衬底内的嵌入式应力元件（33）。 每个嵌入式应力元件包括从底部到顶部具有不同于半导体衬底的晶格常数的晶格常数的第一外延掺杂半导体材料（35）的第一层，并且在器件沟道中施加应变， 位于第一层顶部的第二外延掺杂半导体材料（36）的第二层和位于第二层的上表面上的掺杂剂的Δ单层。 该结构还包括直接位于三角单层（37）的上表面上的金属半导体合金接触（45）。

公开(公告)号：WO2008014228A3

公开(公告)日：2008-09-04

申请号：PCT/US2007074169

申请日：2007-07-24

Applicant: IBM ,  CHAKRAVARTI ASHIMA B ,  CHIDAMBARRAO DURESETI ,  HOLT JUDSON R ,  LIU YAOCHENG ,  RIM KERN

Inventor： CHAKRAVARTI ASHIMA B ,  CHIDAMBARRAO DURESETI ,  HOLT JUDSON R ,  LIU YAOCHENG ,  RIM KERN

IPC: H01L21/336

CPC classification number: H01L21/823864 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/7843 ,  H01L29/7848

Abstract: An embedded silicon carbon (Si:C) having a substitutional carbon content in excess of one percent in order to effectively increase electron mobility by application of tension to a channel region of an NFET is achieved by overfilling a gap or trench formed by transistor gate structures with Si: C and polishing an etching the Si: C to or below a surface of a raised gate structure in a super-Damascene process, leaving Si:C only in selected regions above the transistor source and drain, even though processes capable of depositing Si: C with sufficiently high substitutional carbon content are inherently non-selective.

Abstract translation: 为了通过向NFET的沟道区施加张力而有效地增加电子迁移率，具有超过1％的替代碳含量的嵌入式硅碳（Si：C）通过过度填充由晶体管栅极结构形成的间隙或沟槽来实现 与Si：C并且在超级大马士革工艺中将Si：C蚀刻到凸起栅极结构的表面或其下方，即使能够沉积的工艺仅在晶体管源极和漏极之上的选定区域中留下Si：C 具有足够高取代碳含量的Si：C本质上是非选择性的。

公开(公告)号：SG143174A1

公开(公告)日：2008-06-27

申请号：SG2007178007

申请日：2007-11-16

Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM

Inventor： FU CHONG YUNG ,  ZHIJIONG LUO ,  HOLT JUDSON R

Abstract: Method to form selective strained Si using lateral epitaxy Embodiments for FET devices with stress on the channel region by forming stressor regions under the source/drain regions or the channel region and forming a selective strained Si using lateral epitaxy over the stressor regions. In a first example embodiment, a lateral epitaxial layer is formed over a stressor region under a channel region of an FET. In a second example embodiment, a lateral S/D epitaxial layer is formed over S/D stressor region under the source/drain regions of an FET. In a third example embodiment, both PFET and NFET devices are formed. In the PFET device, a lateral S/D epitaxial layer is formed over S/D stressor region under the source/drain regions. In the NFET device, the lateral epitaxial layer is formed over a stressor region under a channel region of the NFET.