-
公开(公告)号：JPS6149242A
公开(公告)日：1986-03-11
申请号：JP17444185
申请日：1985-08-09
Applicant: Ibm
Inventor： AUSLANDER MARC ALAN , COCKE JOHN , MARKSTEIN PETER WILLY
CPC classification number: G06F8/443
-
公开(公告)号：DE3751306D1
公开(公告)日：1995-06-22
申请号：DE3751306
申请日：1987-10-27
Applicant: IBM
Inventor： COCKE JOHN , MARKSTEIN PETER WILLY
-
公开(公告)号：BR9002995A
公开(公告)日：1991-08-20
申请号：BR9002995
申请日：1990-06-26
Applicant: IBM
Inventor： JANCZYN JOYCE MARIE , MARKSTEIN PETER WILLY
IPC: G06F9/45
Abstract: The present invention relates to a method, in an optimising compiler using specified optimisation procedures for identifying ways of improving the quality of compiled code, for performing preliminary optimising procedures on a program to be compiled, prior to carrying out any specified optimisation procedure. According to the invention the preliminary optimising procedures comprise: (a) developing a control flowgraph representing all possible execution paths for the program; (b) identifying subgraphs in the program; (c) performing the steps of: (1) selecting a subgraph to be examined for the optimisation procedure, the first subgraph on a first iteration being the entire program; (2) by examining the code sequences in the subgraph, determining the number of entities in the subgraph which are relevant to each dimension of arrays used in the specified procedure to represent data flow equations; (3) determining the amount of memory required to contain the arrays; (4) if the amount of memory exceeds a predetermined memory usage limit for the compilation thereby denoting an unsuccessful attempt at the optimisation procedure, applying step (5) to the subgraph, otherwise applying the optimisation procedure to the subgraph, and (5) applying steps (2) to (4) for every subgraph contained in the subgraph for which insufficient memory was found in step (4). a
-
公开(公告)号：CA2010056C
公开(公告)日：1998-05-12
申请号：CA2010056
申请日：1990-02-14
Applicant: IBM , IBM CANADA
Inventor： MARKSTEIN PETER WILLY , O'BRIEN J KEVIN , HALL CHARLES BRIAN
Abstract: This invention provides a process within an optimizing compiler for transforming code to take advantage of update instructions available on some computer architectures. On architectures which implement some form of autoindexing instructions or addressing modes, this process will improve the code generated for looping constructs which manipulate arrays in memory. The process is achieved by selecting memory referencing instructions inside loops for conversion to update forms, modifying those instructions to an update form available on a particular processor, and applying an offset compensation to other memory referencing instructions in the loop so as to enable the program to still address the appropriate locations while using the available autoindexing instructions. The improved compiler and compiler process enables the compiler to convert those program instructions that would otherwise convert to autoindexing instructions not supported by the processor to autoindexing instructions that are supported.
-
公开(公告)号：DE3485929T2
公开(公告)日：1993-04-01
申请号：DE3485929
申请日：1984-05-30
Applicant: IBM
Inventor： AUSLANDER MARC ALAN , COCKE JOHN , HAO HSIEH TUNG , MARKSTEIN PETER WILLY , RADIN GEORGE
Abstract: @ A mechanism including an expanded condition register for use in a reduced instruction set computing system which facilitates the performance of single machine cycle instructions on the system and further provides for the efficient execution of more complex instructions which are not susceptible of being completed in a single machine cycle. More particularly, a mechanism is provided for setting the bits of the expanded condition register whereby a more efficient restart is possible after a machine interrupt and whereby the results of intermediate operations of certain multistep logic and arithmetic operations are maintained in the condition register in order that the cycle time of such multistep operations may be kept to a minimum, and when necessary, may be executed with greater efficiency. Still more particularly, the condition register architecture provides for the efficient handling of multiply and divide operations and provides for the more efficient execution of certain decimal operations within such a reduced instruction set host computer system.
-
Patent Agency Ranking
公开(公告)号：DE3481560D1
公开(公告)日：1990-04-12
申请号：DE3481560
申请日：1984-05-30
Applicant: IBM
Inventor： AUSLANDER MARC ALAN , COCKE JOHN , HAO HSIEH TUNG , MARKSTEIN PETER WILLY , RADIN GEORGE
Abstract: @ A mechanism for performing a run-time storage ad-dress validity check within one machine cycle. The mechanism, functioning together with an intelligent compiler, eliminates the need for hardware implementation of a storage validity check. More particularly, the mechanism performs its function in one machine cycle in the event that a trap exception does not cause an interrupt. In the rare instance when an interrupt is necessary, a number of machine cycles will be impacted. The mechanism comprises a minimum amount of logic circuitry (52) for determining the trap condition operating in conjunction with conventional, previously existing compare, branch instruction testing, and interrupt generation circuitry.
-
公开(公告)号：DE3751306T2
公开(公告)日：1996-01-25
申请号：DE3751306
申请日：1987-10-27
Applicant: IBM
Inventor： COCKE JOHN , MARKSTEIN PETER WILLY
-
公开(公告)号：DE3586374T2
公开(公告)日：1993-03-04
申请号：DE3586374
申请日：1985-07-16
Applicant: IBM
Inventor： AUSLANDER MARC ALAN , COCKE JOHN , MARKSTEIN PETER WILLY
-
公开(公告)号：DE3685149D1
公开(公告)日：1992-06-11
申请号：DE3685149
申请日：1986-02-14
Applicant: IBM
Inventor： COCK JOHN , MARKSTEIN PETER WILLY , MARKSTEIN VICTORIA IRENE
Abstract: A method operable within an optimizing compiler to move certain range check instructions out of single entry strongly connected regions or loops and into linear regions of the instruction stream whereby computational efficiency is increased with no loss of program accuracy. The method comprises placing a range check trap instruction into the header node of the SCR provided there is only one conditional exit from the SCR, modifying the conditional exit test based on the value of the induction variable v, and inserting a new check at the loop exit point(s) to insure that the induction variable has reached the value it would have obtained in the original (unmodified) program.
-
公开(公告)号：DE2758152A1
公开(公告)日：1978-07-13
申请号：DE2758152
申请日：1977-12-27
Applicant: IBM
Inventor： MARKSTEIN PETER WILLY , TRITTER ALAN LEVI
Abstract: A computer system organization which allows a program to specify a predetermined security level for other programs which it invokes, while at the same time being subject to security restraints placed on it either by a higher priority level invoking program or by the operating system. A plurality of security levels organized as a hierarchy which may be established by both problem programmers, and the operating system are then controlled by the operating system. A program cannot change its previously assigned level. Only a higher level invoking program can make such an alteration. A new program's security level indicator must be validated and then a protection code or 'mask' of a predetermined size related to the security level must be validated. The system utilizes a plurality of special purpose bits in every data word which bits contain the protection field. Level indicators for the particular program determine the use of the protection field. A series of linking registers or a 'Link Stack' having appropriate logic circuitry connected thereto is utilized for keeping track of the security level of all programs in a hierarchical sequence currently running on the system. The stack allows proper branching back to an originating program and prevents violation of security rules. The hardware additionally provides a mechanism for automatically checking each and every memory access, whether read or write, to assure that a correct protection field is present in each of the memory data words which is to be accessed or stored into.
-
-
-
-
-
-
-
-
-
Search Results
17
records
(took 0.017 seconds)
