公开(公告)号：CA2080608A1

公开(公告)日：1993-07-03

申请号：CA2080608

申请日：1992-10-15

Applicant: IBM

Inventor： AMINI NADER ,  BOURY BECHARA F ,  BRANNON SHERWOOD ,  HORNE RICHARD L ,  LOHMAN TERENCE J

IPC: G06F13/36 ,  G06F13/16 ,  G06F13/18 ,  G06F13/20

Abstract: BC9-91-089 BUS CONTROL LOGIC FOR COMPUTER SYSTEM HAVING DUAL BUS ARCHITECTURE A computer system is provided, comprising system memory and a memory controller for controlling access to system memory by means of a memory bus, a central processing unit electrically connected with the memory controller for reading and writing data to the system memory over the memory bus, a bus interface unit electrically connected with the memory controller by means of a system bus, and an input/output device electrically connected to the bus interface unit by an input/output bus. The memory controller incorporates logic for arbitrating between the central processing unit and the input/output device to determine which of the central processing unit and the input/output device should be granted access to the system memory through said memory bus. The bus interface unit incorporates logic for overriding the memory controller logic, in response to a series of predetermined operating conditions, and grant exclusive access to system memory to the input/output device.

公开(公告)号：CA2080210A1

公开(公告)日：1993-07-03

申请号：CA2080210

申请日：1992-10-08

Applicant: IBM

Inventor： AMINI NADER ,  BOURY BECHARA F ,  BRANNON SHERWOOD ,  HORNE RICHARD L ,  LOHMAN TERENCE J

IPC: G06F13/28 ,  G06F13/16 ,  G06F13/40

Abstract: The present invention provides a bus to bus interface unit for computer systems having dual bus architecture, such as a system bus and an I/O bus. The bus interface unit includes an asynchronous bidirectional temporary data storage function for data being transferred between the two buses to and from devices coupled to each of the two buses. Preferably the storage function operates in modes that will accommodate individual transfers of data, data streaming, and data burst transfers, and can accommodate transfers of information from contiguous addresses without initiating a new request for each address.

公开(公告)号：BR9205015A

公开(公告)日：1993-07-06

申请号：BR9205015

申请日：1992-12-15

Applicant: IBM

Inventor： AMINI NADER ,  BOURY BECHARA F ,  BRANNON SHERWOOD ,  HORNE RICHARD L ,  LOHMAN TERENCE J

IPC: G06F13/28 ,  G06F13/16 ,  G06F13/40 ,  G06F3/00

Abstract: The present invention provides a bus to bus interface unit for computer systems having dual bus architecture, such as a system bus and an I/O bus. The bus interface unit includes an asynchronous bidirectional temporary data storage function for data being transferred between the two buses to and from devices coupled to each of the two buses. Preferably the storage function operates in modes that will accommodate individual transfers of data, data streaming, and data burst transfers, and can accommodate transfers of information from contiguous addresses without initiating a new request for each address.

公开(公告)号：CA2080630A1

公开(公告)日：1993-07-03

申请号：CA2080630

申请日：1992-10-15

Applicant: IBM

Inventor： AMINI NADER ,  BOURY BECHARA F ,  HORNE RICHARD L ,  LOHMAN TERENCE J

IPC: G06F13/28 ,  G06F13/22 ,  G06F13/36 ,  G06F13/362

Abstract: A computer system is provided comprising system memory and a memory controller for controlling access to system memory, a central processing unit electrically connected with the memory controller, and a bus interface unit electrically connected to the memory controller by a system bus and electrically connected to a plurality of input/output devices by an input/output bus. The bus interface unit is able to sense when said one of said input/output devices has completed a read or write operation over said input/output bus, and includes a buffer circuit wherein read and write data transferred between the system bus and the input/output bus via the bus interface unit is temporarily stored during the transfer. Arbitration control logic resides in said bus interface unit and interacts with a central arbitration controller which resides on the system bus. The central arbitration controller responds to the arbitration control logic to simultaneously perform (i) arbitration cycles wherein the central arbitration controller arbitrates between the plurality of input/output devices and the central processing unit to determine which of the input/output devices or the central processing unit should be granted control of the input/output bus and (ii) grant cycles wherein the central arbitration controller grants control of the input/output bus and extends control of the system bus to one of the input/output devices or the central processing unit.