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    Bus control logic for computer system having dual bus architecture
    1.
    发明专利
    Bus control logic for computer system having dual bus architecture 未知

    公开(公告)号：AU663536B2

    公开(公告)日：1995-10-12

    申请号：AU2979292

    申请日：1992-12-02

    Applicant: IBM

    Inventor： AMINI NADER ,  BOURY BECHARA FOUAD ,  BRANNON SHERWOOD ,  HORNE RICHARD LOUIS ,  LOHMAN TERENCE JOSEPH

    IPC: G06F13/36 ,  G06F13/16 ,  G06F13/18 ,  G06F13/14

    Abstract: A computer system is provided, comprising system memory and a memory controller for controlling access to system memory by means of a memory bus, a central processing unit electrically connected with the memory controller for reading and writing data to the system memory over the memory bus, a bus interface unit electrically connected with the memory controller by means of a system bus, and an input/output device electrically connected to the bus interface unit by an input/output bus. The memory controller incorporates logic for arbitrating between the central processing unit and the input/output device to determine which of the central processing unit and the input/output device should be granted access to the system memory through said memory bus. The bus interface unit incorporates logic for overriding the memory controller logic, in response to a series of predetermined operating conditions, and grant exclusive access to system memory to the input/output device.

    BUS CONTROL LOGIC OVERRIDES MEMORY ARBITRATION CONTROL LOGIC FOR DUAL BUS ARCHITECTURE COMPUTER
    2.
    发明专利
    BUS CONTROL LOGIC OVERRIDES MEMORY ARBITRATION CONTROL LOGIC FOR DUAL BUS ARCHITECTURE COMPUTER 未知

    公开(公告)号：NZ245344A

    公开(公告)日：1995-09-26

    申请号：NZ24534492

    申请日：1992-12-02

    Applicant: IBM

    Inventor： AMINI NADER ,  BOURY BECHARA FOUAD ,  BRANNON SHERWOOD ,  HORNE RICHARD LOUIS ,  LOHMAN TERRENCE JOSEPH

    IPC: G06F13/36 ,  G06F13/16 ,  G06F15/76

    Abstract: A computer system is provided, comprising system memory and a memory controller for controlling access to system memory by means of a memory bus, a central processing unit electrically connected with the memory controller for reading and writing data to the system memory over the memory bus, a bus interface unit electrically connected with the memory controller by means of a system bus, and an input/output device electrically connected to the bus interface unit by an input/output bus. The memory controller incorporates logic for arbitrating between the central processing unit and the input/output device to determine which of the central processing unit and the input/output device should be granted access to the system memory through said memory bus. The bus interface unit incorporates logic for overriding the memory controller logic, in response to a series of predetermined operating conditions, and grant exclusive access to system memory to the input/output device.

    BIDIRECTIONAL DATA STORAGE FACILITY FOR BUS INTERFACE UNIT
    3.
    发明专利
    BIDIRECTIONAL DATA STORAGE FACILITY FOR BUS INTERFACE UNIT 未知

    公开(公告)号：CA2080210A1

    公开(公告)日：1993-07-03

    申请号：CA2080210

    申请日：1992-10-08

    Applicant: IBM

    Inventor： AMINI NADER ,  BOURY BECHARA F ,  BRANNON SHERWOOD ,  HORNE RICHARD L ,  LOHMAN TERENCE J

    IPC: G06F13/28 ,  G06F13/16 ,  G06F13/40

    Abstract: The present invention provides a bus to bus interface unit for computer systems having dual bus architecture, such as a system bus and an I/O bus. The bus interface unit includes an asynchronous bidirectional temporary data storage function for data being transferred between the two buses to and from devices coupled to each of the two buses. Preferably the storage function operates in modes that will accommodate individual transfers of data, data streaming, and data burst transfers, and can accommodate transfers of information from contiguous addresses without initiating a new request for each address.

    EXPANDABLE HIGH PERFORMANCE FIFO DESIGN
    4.
    发明专利
    EXPANDABLE HIGH PERFORMANCE FIFO DESIGN 未知

    公开(公告)号：CA2071347A1

    公开(公告)日：1993-04-16

    申请号：CA2071347

    申请日：1992-06-16

    Applicant: IBM

    Inventor： AMINI NADER ,  BOURY BECHARA F ,  BRANNON SHERWOOD ,  LOHMAN TERENCE J

    IPC: G06F12/00 ,  G06F5/06 ,  G11C7/00 ,  G06F13/16

    Abstract: BC9-91-072 EXPANDABLE HIGH PERFORMANCE FIFO DESIGN An arrangement of cells with input and output steering circuitry as well as internal shifting capabilities is disclosed which advantageously provides a first in/first out (FIFO) register circuit which can be written to and read from in contiguous clock cycles. The FIFO register circuit is provided with an arrangement of self contained FIFO cells, each cell containing its own input multiplexer and control circuitry.

    BIDIRECTIONAL DATA STORAGE FACILITY FOR BUS INTERFACE UNIT
    7.
    发明专利
    BIDIRECTIONAL DATA STORAGE FACILITY FOR BUS INTERFACE UNIT 未知

    公开(公告)号：CA2080210C

    公开(公告)日：1998-10-27

    申请号：CA2080210

    申请日：1992-10-08

    Applicant: IBM

    Inventor： LOHMAN TERENCE JOSEPH ,  AMINI NADER ,  BOURY BECHARA FOUAD ,  BRANNON SHERWOOD ,  HORNE RICHARD LOUIS

    IPC: G06F13/28 ,  G06F13/16 ,  G06F13/40

    Abstract: The present invention provides a bus to bus interface unit for computer systems having dual bus architecture, such as a system bus and an I/O bus. The bus interface unit includes an asynchronous bidirectional temporary data storage function for data being transferred between the two buses to and from devices coupled to each of the two buses. Preferably the storage function operates in modes that will accommodate individual transfers of data, data streaming, and data burst transfers, and can accommodate transfers of information from contiguous addresses without initiating a new request for each address.

    BUS CONTROL LOGIC FOR COMPUTER SYSTEM HAVING DUAL BUS ARCHITECTURE
    9.
    发明专利
    BUS CONTROL LOGIC FOR COMPUTER SYSTEM HAVING DUAL BUS ARCHITECTURE 未知

    公开(公告)号：CA2080608A1

    公开(公告)日：1993-07-03

    申请号：CA2080608

    申请日：1992-10-15

    Applicant: IBM

    Inventor： AMINI NADER ,  BOURY BECHARA F ,  BRANNON SHERWOOD ,  HORNE RICHARD L ,  LOHMAN TERENCE J

    IPC: G06F13/36 ,  G06F13/16 ,  G06F13/18 ,  G06F13/20

    Abstract: BC9-91-089 BUS CONTROL LOGIC FOR COMPUTER SYSTEM HAVING DUAL BUS ARCHITECTURE A computer system is provided, comprising system memory and a memory controller for controlling access to system memory by means of a memory bus, a central processing unit electrically connected with the memory controller for reading and writing data to the system memory over the memory bus, a bus interface unit electrically connected with the memory controller by means of a system bus, and an input/output device electrically connected to the bus interface unit by an input/output bus. The memory controller incorporates logic for arbitrating between the central processing unit and the input/output device to determine which of the central processing unit and the input/output device should be granted access to the system memory through said memory bus. The bus interface unit incorporates logic for overriding the memory controller logic, in response to a series of predetermined operating conditions, and grant exclusive access to system memory to the input/output device.

    10.
    发明专利
    未知

    公开(公告)号：BR9203585A

    公开(公告)日：1993-04-27

    申请号：BR9203585

    申请日：1992-09-15

    Applicant: IBM

    Inventor： AMINI NADER ,  BOURY BECHARA F ,  BRANNON SHERWOOD ,  LOHMAN TERENCE J

    IPC: G06F12/00 ,  G06F5/06 ,  G11C7/00

    Abstract: An arrangement of cells with input and output steering circuitry as well as internal shifting capabilities is disclosed which advantageously provides a first in/first out (FIFO) register circuit which can be written to and read from in contiguous clock cycles. The FIFO register circuit is provided with an arrangement of self contained FIFO cells, each cell containing its own input multiplexer and control circuitry.

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