公开(公告)号：CA2080608A1

公开(公告)日：1993-07-03

申请号：CA2080608

申请日：1992-10-15

Applicant: IBM

Inventor： AMINI NADER ,  BOURY BECHARA F ,  BRANNON SHERWOOD ,  HORNE RICHARD L ,  LOHMAN TERENCE J

IPC: G06F13/36 ,  G06F13/16 ,  G06F13/18 ,  G06F13/20

Abstract: BC9-91-089 BUS CONTROL LOGIC FOR COMPUTER SYSTEM HAVING DUAL BUS ARCHITECTURE A computer system is provided, comprising system memory and a memory controller for controlling access to system memory by means of a memory bus, a central processing unit electrically connected with the memory controller for reading and writing data to the system memory over the memory bus, a bus interface unit electrically connected with the memory controller by means of a system bus, and an input/output device electrically connected to the bus interface unit by an input/output bus. The memory controller incorporates logic for arbitrating between the central processing unit and the input/output device to determine which of the central processing unit and the input/output device should be granted access to the system memory through said memory bus. The bus interface unit incorporates logic for overriding the memory controller logic, in response to a series of predetermined operating conditions, and grant exclusive access to system memory to the input/output device.

公开(公告)号：BR9203585A

公开(公告)日：1993-04-27

申请号：BR9203585

申请日：1992-09-15

Applicant: IBM

Inventor： AMINI NADER ,  BOURY BECHARA F ,  BRANNON SHERWOOD ,  LOHMAN TERENCE J

IPC: G06F12/00 ,  G06F5/06 ,  G11C7/00

Abstract: An arrangement of cells with input and output steering circuitry as well as internal shifting capabilities is disclosed which advantageously provides a first in/first out (FIFO) register circuit which can be written to and read from in contiguous clock cycles. The FIFO register circuit is provided with an arrangement of self contained FIFO cells, each cell containing its own input multiplexer and control circuitry.

公开(公告)号：CA2124031A1

公开(公告)日：1994-11-29

申请号：CA2124031

申请日：1994-05-20

Applicant: IBM

Inventor： AMINI NADER ,  BLAND PATRICK M ,  BOURY BECHARA F ,  HOFMANN RICHARD G ,  LOHMAN TERENCE J

IPC: G06F13/28 ,  G06F13/30 ,  G06F13/36 ,  G06F13/40 ,  G06F13/14

Abstract: A direct memory access (DMA) support mechanism is provided for use in a computer system 10 which comprises (i) a central processing unit (CPU) 24 connected to system memory 32 by a first system bus 36, and a second system bus 16 connected to the CPU; (ii) a host bridge 20 connecting the second system bus to a peripheral bus 22; (iii) an input/output (I/O) bridge 78 connecting the peripheral bus to a standard I/O bus 92, the standard I/O bus having a plurality of standard I/O devices 90 attached thereto; and (v) arbitration logic 42 which functions in an arbitration mode for arbitrating between the plurality of standard I/O devices competing for access to the standard I/O bus, and in a grant mode wherein a selected standard I/O device is granted access to the standard I/O bus. The DMA support mechanism comprises a direct memory access (DMA) controller 40 for performing DMA cycles on behalf of the selected standard I/O device, and direct memory access (DMA) support logic for enabling the DMA cycles to be performed over the peripheral bus. The DMA support logic includes sideband signals directly connecting the DMA controller with the I/O bridge, the sideband signals including information identifying the bus size of the selected I/O device for which the DMA controller is performing the DMA cycles.

公开(公告)号：CA2080210A1

公开(公告)日：1993-07-03

申请号：CA2080210

申请日：1992-10-08

Applicant: IBM

Inventor： AMINI NADER ,  BOURY BECHARA F ,  BRANNON SHERWOOD ,  HORNE RICHARD L ,  LOHMAN TERENCE J

IPC: G06F13/28 ,  G06F13/16 ,  G06F13/40

Abstract: The present invention provides a bus to bus interface unit for computer systems having dual bus architecture, such as a system bus and an I/O bus. The bus interface unit includes an asynchronous bidirectional temporary data storage function for data being transferred between the two buses to and from devices coupled to each of the two buses. Preferably the storage function operates in modes that will accommodate individual transfers of data, data streaming, and data burst transfers, and can accommodate transfers of information from contiguous addresses without initiating a new request for each address.

公开(公告)号：BR9203811A

公开(公告)日：1993-04-27

申请号：BR9203811

申请日：1992-09-30

Applicant: IBM

Inventor： AMINI NADER ,  BOURY BECHARA F ,  LOHMAN TERENCE J

IPC: G06F13/36 ,  G06F13/30 ,  G06F13/362 ,  G06F13/00

Abstract: An arbiter with an arbitration hold feature is discloses which makes it possible to begin an arbitration cycle while information is still being transferred via a bus because the arbiter does not reallocate the bus until the present transfer is complete, as indicated by the arbitration hold feature. Accordingly, arbitration can essentially be overlapped with transfer of information over the bus, thus increasing the amount of information which can be transferred in a given interval of time.

公开(公告)号：CA2071376A1

公开(公告)日：1993-04-16

申请号：CA2071376

申请日：1992-06-16

Applicant: IBM

Inventor： AMINI NADER ,  BOURY BECHARA F ,  LOHMAN TERENCE J

IPC: G06F13/36 ,  G06F13/30 ,  G06F13/362 ,  G06F13/12 ,  G06F13/18

Abstract: BC9-91-082 CONTROLLING BUS ALLOCATION USING ARBITRATION HOLD An arbiter with an arbitration hold feature is discloses which makes it possible to begin an arbitration cycle while information is still being transferred via a bus because the arbiter does not reallocate the bus until the present transfer is complete, as indicated by the arbitration hold feature. Accordingly, arbitration can essentially be overlapped with transfer of information over the bus, thus increasing the amount of information which can be transferred in a given interval of time.

公开(公告)号：CA2071347A1

公开(公告)日：1993-04-16

申请号：CA2071347

申请日：1992-06-16

Applicant: IBM

Inventor： AMINI NADER ,  BOURY BECHARA F ,  BRANNON SHERWOOD ,  LOHMAN TERENCE J

IPC: G06F12/00 ,  G06F5/06 ,  G11C7/00 ,  G06F13/16

Abstract: BC9-91-072 EXPANDABLE HIGH PERFORMANCE FIFO DESIGN An arrangement of cells with input and output steering circuitry as well as internal shifting capabilities is disclosed which advantageously provides a first in/first out (FIFO) register circuit which can be written to and read from in contiguous clock cycles. The FIFO register circuit is provided with an arrangement of self contained FIFO cells, each cell containing its own input multiplexer and control circuitry.

公开(公告)号：CA2118995A1

公开(公告)日：1994-11-29

申请号：CA2118995

申请日：1994-03-14

Applicant: IBM

Inventor： AMINI NADER ,  BLAND PATRICK M ,  BOURY BECHARA F ,  HOFMANN RICHARD G ,  LOHMAN TERENCE J

IPC: G06F13/36 ,  G06F13/362 ,  G06F13/364 ,  G06F13/40

Abstract: An arbitration mechanism 42 is provided for use in a computer system 10 which comprises (i) a central processing unit (CPU) 24; (ii) a first system bus 36 which connects the CPU 24 to system memory 32 so that the CPU 24 can read data from, and write data to, the system memory 32; (iii) a second system bus 16 connected to the CPU 24; (iv) a host bridge 20 connecting the second-system bus 16 to a peripheral bus 22, the peripheral bus 22 having at least one peripheral device 18 attached thereto; and (v) an input/output (I/O) bridge 78 connecting the peripheral bus 22 to a standard I/O bus 92, the standard I/O bus 92 having a plurality of standard I/O devices 90 attached thereto. The arbitration mechanism 42 comprises (i) a first level 100 of logic for arbitrating between the plurality of standard I/O devices 90, wherein one standard I/O device 90 is selected from a plurality of the standard I/O devices 90 competing for access to the standard I/O bus 97, and (ii) a second level 102, 104 of logic for arbitrating between the selected standard I/O device 90, the CPU 24 and the at least one peripheral device 18, wherein one of the selected standard I/O device 90, the CPU 24 and the at least one peripheral device 18 is selected to access the peripheral bus 22. The arbitration mechanism 42 includes sideband signals which connect the first 100 and second levels 102, 104 of arbitration logic and include arbitration identification information corresponding to the selected standard I/O device 90.

公开(公告)号：BR9205015A

公开(公告)日：1993-07-06

申请号：BR9205015

申请日：1992-12-15

Applicant: IBM

Inventor： AMINI NADER ,  BOURY BECHARA F ,  BRANNON SHERWOOD ,  HORNE RICHARD L ,  LOHMAN TERENCE J

IPC: G06F13/28 ,  G06F13/16 ,  G06F13/40 ,  G06F3/00

Abstract: The present invention provides a bus to bus interface unit for computer systems having dual bus architecture, such as a system bus and an I/O bus. The bus interface unit includes an asynchronous bidirectional temporary data storage function for data being transferred between the two buses to and from devices coupled to each of the two buses. Preferably the storage function operates in modes that will accommodate individual transfers of data, data streaming, and data burst transfers, and can accommodate transfers of information from contiguous addresses without initiating a new request for each address.

公开(公告)号：CA2080630A1

公开(公告)日：1993-07-03

申请号：CA2080630

申请日：1992-10-15

Applicant: IBM

Inventor： AMINI NADER ,  BOURY BECHARA F ,  HORNE RICHARD L ,  LOHMAN TERENCE J

IPC: G06F13/28 ,  G06F13/22 ,  G06F13/36 ,  G06F13/362

Abstract: A computer system is provided comprising system memory and a memory controller for controlling access to system memory, a central processing unit electrically connected with the memory controller, and a bus interface unit electrically connected to the memory controller by a system bus and electrically connected to a plurality of input/output devices by an input/output bus. The bus interface unit is able to sense when said one of said input/output devices has completed a read or write operation over said input/output bus, and includes a buffer circuit wherein read and write data transferred between the system bus and the input/output bus via the bus interface unit is temporarily stored during the transfer. Arbitration control logic resides in said bus interface unit and interacts with a central arbitration controller which resides on the system bus. The central arbitration controller responds to the arbitration control logic to simultaneously perform (i) arbitration cycles wherein the central arbitration controller arbitrates between the plurality of input/output devices and the central processing unit to determine which of the input/output devices or the central processing unit should be granted control of the input/output bus and (ii) grant cycles wherein the central arbitration controller grants control of the input/output bus and extends control of the system bus to one of the input/output devices or the central processing unit.