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公开(公告)号：DE2965742D1
公开(公告)日：1983-07-28
申请号：DE2965742
申请日：1979-09-24
Applicant: IBM
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公开(公告)号：IT7926081D0
公开(公告)日：1979-09-28
申请号：IT2608179
申请日：1979-09-28
Applicant: IBM
Inventor： MITCHELL GLEN ROBERT , SOLTIS FRANK GERALD , HOFFMAN ROY LOUIS
Abstract: Virtual addressing apparatus for implementing a large virtual address in a computer system having narrow data paths, ALU, and local storage register arrays without requiring multiple passes. The virtual addressing apparatus stores the segment portion of a virtual address in a segment register and the offset portion of the virtual address in an offset register. To form a new virtual address, a new offset value is obtained by adding the displacement value given by the instruction in the instruction buffer register to the offset value stored in the offset register. The segment portion of the virtual address does not participate in the arithmetic operation for forming the new virtual address. The segment and offset portions are concatenated to form the new virtual address which is then translated to a main store address. Overflow detection circuitry in the ALU detects if an overflow out of the offset occurs as a result of the ALU operation for obtaining the new offset value. If an overflow is detected during the calculation of the new offset value, translation of the virtual address is subsequently aborted.
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公开(公告)号：DE3273912D1
公开(公告)日：1986-11-27
申请号：DE3273912
申请日：1982-03-09
Applicant: IBM
Inventor： HOFFMAN ROY LOUIS , HOUDEK MERLE EDWARD , LOEN LARRY WAYNE , SOLTIS FRANK GERALD
IPC: G06F9/46 , G06F9/48 , G06F15/16 , G06F15/177
Abstract: The task handling arrangement is provided in a multiprocessor system in which each processor (5) includes a task dispatcher and a signal dispatcher. The signal dispatcher runs in a processor whenever a task dispatching element (TDE) is put on the task dispatching queue (TDQ) as a result of the task running in the processor. The signal dispatcher examines the TDEs enqueued on the TDQ and determines if any task dispatcher should be invoked, i.e. if any processor is running a lower priority task a task switch should occur. If so, it signals the selected processor to invoke its task dispatcher. After completing the task switch, the selected processor must invoke its signal dispatcher to determine if the task it had been performing should now be performed on some other processor in the multiprocessor system.
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公开(公告)号：DE2963499D1
公开(公告)日：1982-09-30
申请号：DE2963499
申请日：1979-09-24
Applicant: IBM
Inventor： MITCHELL GLEN ROBERT , SOLTIS FRANK GERALD , HOFFMAN ROY LOUIS
Abstract: Virtual addressing apparatus for implementing a large virtual address in a computer system having narrow data paths, ALU, and local storage register arrays without requiring multiple passes. The virtual addressing apparatus stores the segment portion of a virtual address in a segment register and the offset portion of the virtual address in an offset register. To form a new virtual address, a new offset value is obtained by adding the displacement value given by the instruction in the instruction buffer register to the offset value stored in the offset register. The segment portion of the virtual address does not participate in the arithmetic operation for forming the new virtual address. The segment and offset portions are concatenated to form the new virtual address which is then translated to a main store address. Overflow detection circuitry in the ALU detects if an overflow out of the offset occurs as a result of the ALU operation for obtaining the new offset value. If an overflow is detected during the calculation of the new offset value, translation of the virtual address is subsequently aborted.
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公开(公告)号：DE2963099D1
公开(公告)日：1982-08-05
申请号：DE2963099
申请日：1979-06-11
Applicant: IBM
Inventor： HOFFMAN ROY LOUIS , MITCHELL GLEN ROBERT , SOLTIS FRANK GERALD
Abstract: Address translation apparatus is provided for translating virtual addresses to real storage addresses and real storage addresses to virtual storage addresses. The address translation apparatus uses a page directory having a next real address and an associated virtual address ordered according to real addresses. This simplifies the manner in which the input/output (I/O) handles addressing in a virtual storage computer system. When the I/O device control mechanism needs to resolve the real I/O address register, it uses the contents of that register to index into the page directory to obtain a corresponding virtual address. The corresponding virtual address is incremented and converted to a real address which is used to index into the page directory. The virtual address taken from the page directory is then compared with the virtual address which had been incremented and translated. If the two compare then the real address which had been used to access the page directory is entered into a register so as to be available as a real main storage address. In actuality it is only a partial real main storage address and is concantenated with a byte identifier portion of the main storage address which requires no translation and which was a part of the original I/O real address for main storage.
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Patent Agency Ranking
公开(公告)号：DE2702722A1
公开(公告)日：1977-08-11
申请号：DE2702722
申请日：1977-01-24
Applicant: IBM
Inventor： HOFFMAN ROY LOUIS , KEMPKE WILLIAM GEORGE , SOLTIS FRANK GERALD
Abstract: A special directly executable instruction, Fetch Instruction Operand Address (FIOA) is accessed in response to encountering a complex non-directly executable instruction. Execution of the FIOA instruction causes generation of control signals for address calculation of the operands in the non-directly executable instruction by the same I phase hardware used by other directly executable instructions.
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公开(公告)号：DE3480129D1
公开(公告)日：1989-11-16
申请号：DE3480129
申请日：1984-02-20
Applicant: IBM
Inventor： HOFFMAN ROY LOUIS , HOUDEK MERLE EDWARD , SOLTIS FRANK GERALD
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