公开(公告)号：EP1946200A4

公开(公告)日：2008-11-26

申请号：EP06787992

申请日：2006-07-19

Applicant: IBM

Inventor： BOSE PRADIP ,  BUYUKTOSUNOGLU ALPER ,  HU ZHIGANG ,  JACOBSON HANS MIKAEL ,  SRINIVASAN VIJAYALAKSHMI ,  ZYUBAN VICTOR

IPC: G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/30145 ,  G06F9/382 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3867 ,  Y02D10/171 ,  Y02D10/24

Abstract: A device for controlling power parameters in a microprocessor includes a resource activation control unit for controlling the maximum power of the microprocessor and two or more resources. The resource activation control unit controls the activation of the resources such that the consumed and dissipated power of the microprocessor does not exceed a power bound which is configurable to a predetermined value below the maximum power.

公开(公告)号：WO2007024374A3

公开(公告)日：2007-09-20

申请号：PCT/US2006028210

申请日：2006-07-19

Applicant: IBM ,  BOSE PRADIP ,  BUYUKTOSUNOGLU ALPER ,  HU ZHIGANG ,  JACOBSON HANS MIKAEL ,  SRINIVASAN VIJAYALAKSHMI ,  ZYUBAN VICTOR

Inventor： BOSE PRADIP ,  BUYUKTOSUNOGLU ALPER ,  HU ZHIGANG ,  JACOBSON HANS MIKAEL ,  SRINIVASAN VIJAYALAKSHMI ,  ZYUBAN VICTOR

IPC: G06F1/00 ,  G06F1/26 ,  G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/30145 ,  G06F9/382 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3867 ,  Y02D10/171 ,  Y02D10/24

Abstract: A device for controlling power parameters in a microprocessor (10) includes a resource activation control unit (12) for controlling the maximum power of the microprocessor (10) and two or more resources (26 1 , 26 2 , 26 3 ). The resource activation control unit (12) controls the activation of the resources (26 1, 26 2 , 26 3 ).such that the consumed and dissipated power of the microprocessor (10) does not exceed a power bound which is configurable to a predetermined value below the maximum power.

Abstract translation: 一种用于控制微处理器（10）中的功率参数的装置包括用于控制微处理器（10）的最大功率和两个或更多个资源（26 1， SUB> 2 ，26 3 3）。 资源激活控制单元（12）控制资源（26 1，...，26，26，3）的激活，使得消耗的 并且微处理器（10）的耗散功率不超过可配置到低于最大功率的预定值的功率限制。

公开(公告)号：WO2008008211A2

公开(公告)日：2008-01-17

申请号：PCT/US2007015189

申请日：2007-06-29

Applicant: IBM ,  BOSE PRADIP ,  HU ZHIGANG ,  LI XIOADONG ,  RIVERS JUDE A

Inventor： BOSE PRADIP ,  HU ZHIGANG ,  LI XIOADONG ,  RIVERS JUDE A

IPC: G06F11/00

CPC classification number: G06F12/0804 ,  G06F11/1497 ,  G06F2212/1032

Abstract: A write filter cache system for protecting a microprocessor core from soft errors and method thereof are provided. In one aspect, data coming from a processor core to be written in primary cache memory, for instance, Ll cache memory system, is buffered in a write filter cache placed between the primary cache memory and the processor core. The data from the write filter is move to the main cache memory only if it is verified that main thread's data is soft error free, for instance, by comparing the main thread's data with that of its redundant thread. The main cache memory only keeps clean data associated with accepted checkpoints.

Abstract translation: 提供了一种用于保护微处理器内核免受软错误的写过滤器高速缓存系统及其方法。 在一个方面，来自处理器核心的要写入主高速缓存存储器（例如，L1缓存存储器系统）的数据被缓存在放置在主高速缓存存储器和处理器核心之间的写入过滤器高速缓存中。 只有在验证主线程的数据是软错误的情况下，例如通过将主线程的数据与其冗余线程的数据进行比较，才将写入过滤器的数据移动到主缓存器。 主缓存只保留与接受检查点关联的干净数据。