公开(公告)号：JPS6384186A

公开(公告)日：1988-04-14

申请号：JP20534287

申请日：1987-08-20

Applicant: IBM

Inventor： HARDER CHRISTOPH STEFAN ,  JAECKEL HEINZ ,  MEIER HEINZ

IPC: H01S5/00 ,  H01S5/042 ,  H01S5/22 ,  H01S5/223 ,  H01S5/30 ,  H01S5/40

公开(公告)号：JPH0553317B2

公开(公告)日：1993-08-09

申请号：JP20534287

申请日：1987-08-20

Applicant: IBM

Inventor： HARDER CHRISTOPH STEFAN ,  JAECKEL HEINZ ,  MEIER HEINZ

IPC: H01S5/00 ,  H01S5/042 ,  H01S5/22 ,  H01S5/223 ,  H01S5/30 ,  H01S5/40 ,  H01S3/18

公开(公告)号：DE3685755D1

公开(公告)日：1992-07-23

申请号：DE3685755

申请日：1986-09-23

Applicant: IBM

Inventor： HARDER CHRISTOPH STEFAN ,  JAECKEL HEINZ ,  MEIER HEINZ

IPC: H01S5/00 ,  H01S5/042 ,  H01S5/22 ,  H01S5/223 ,  H01S5/30 ,  H01S5/40 ,  H01S3/19 ,  H01S3/23

Abstract: In a transverse junction stripe laser (10), comprising a semiconductor substrate (11) supporting a semiconductor heterostructure of an active layer (13) sandwiched between higher bandgap cladding layers (12, 14), the novelty is that (i) the substrate surface has planar regions and inclined regions of different crystallographic indices; (ii) the active and cladding layers are epitaxially grown with an amphoteric dopant such that the layer sections on the planar regions are of first conductivity type and the layer sections on the inclined regions are of second conductivity type, thus forming one or more junctions (15, 16) in the active layer (13); and (ii) ohmic anode (20, 21) and cathode (22) contacts are provided for applying currents (23, 24) of at least threshold level to the junction(s).

公开(公告)号：DE3685755T2

公开(公告)日：1993-02-04

申请号：DE3685755

申请日：1986-09-23

Applicant: IBM

Inventor： HARDER CHRISTOPH STEFAN ,  JAECKEL HEINZ ,  MEIER HEINZ

IPC: H01S5/00 ,  H01S5/042 ,  H01S5/22 ,  H01S5/223 ,  H01S5/30 ,  H01S5/40 ,  H01S3/19 ,  H01S3/23

Abstract: GaAs/AlGaAs-transverse junction stripe (TJS) laser with p-n junction formation by crystal plane dependent doping. The laser structure (10) consists of a molecular beam expitaxy (MBE)-deposited hetero-structure comprising AlGaAs layers (12,14) with an active GaAs layers (13) sandwiched inbetween. These layers are grown on the patterned surface of a GaAs substrate (11) which provides (100)-plane oriented planar ridges and grooves, the edge being (111A)-plane oriented. p-n homojunctions (15 to 18) are formed in the GaAs layer (13) at the intersections of the (111A) and (100) crystal planes. Ohmic contacts (20,21,22) are provided for applying currents (23,24) of at least the threshold level of the junctions. These novel TJS lasers can be used to form 1- or 2-dimensional arrays of phase-coupled lasers for providing high optical power output.

公开(公告)号：DE69228422T2

公开(公告)日：1999-09-30

申请号：DE69228422

申请日：1992-11-24

Applicant: IBM

Inventor： CLAUBERG ROLF ,  HARDER CHRISTOPH ,  HEUSCH CHRISTIAN ,  JAECKEL HEINZ

IPC: G02B6/122 ,  G01C19/66 ,  G02B6/125 ,  G02B6/24 ,  H01S3/00 ,  H01S3/083 ,  H01S5/00 ,  H01S5/026 ,  H01S5/10 ,  G02F1/095 ,  G02B6/12

Abstract: Optical waveguide isolator (121) for monolithic integration with semiconductor light emitting diodes such as Fabry-Perot or ring laser diodes. The present optical isolator (121), with optical input port (95) and output port (96), comprises a branching waveguide coupler (56). This branching waveguide coupler (56) has a waveguide stem (60) splitted at one end into two waveguide branches (57,58) such that a light wave fed via said input port (95) into a first of these branches (58), is guided via the waveguide stem (60) and the output port (96) out of the device. A light wave fed to the isolator's output port (96) is guided along the stem (60) and coupled into the second waveguide branch (57) to the absorber (54).

公开(公告)号：CA1266812A

公开(公告)日：1990-03-20

申请号：CA508352

申请日：1986-05-05

Applicant: IBM

Inventor： HARDER CHRISTOPH S ,  JAECKEL HEINZ ,  WOLF HANS P

IPC: H01L21/338 ,  H01L29/08 ,  H01L29/812 ,  H01L21/20 ,  H01L29/80

Abstract: Method of Fabricating a Self-Aligned Metal-Semiconductor FET A method for the fabrication of self-aligned MESFET structures (30) with a recessed refractory submicron gate. After channel formation (32) on a SI substrate (31), which may consist of a III-V compound semiconductor such as GaAs, with subsequent annealing the refractory gate (33G) is deposited and patterned. This is followed by the overgrowth of a highly doped contact layer of e.g. GaAs using MOCVD or MBE processes resulting in poly-cry-stalline material over the gate "mask" and in mono-cry-stalline material (34S, 34D) on exposed semiconductor surfaces. Next, the poly-crystalline material is removed in a selective etch process, this step being followed by the deposition of source and drain electrodes (35S, 35D). In order to further improve process reliability, insulating sidewalls (43-43) can be provided at the vertical edges of the gate (33G) to avoid source-gate and draingate shorts.