PROCESS FOR FORMING THE RIDGE STRUCTURE OF A SELF-ALIGNED SEMICONDUCTOR LASER

    公开(公告)号:CA2039875C

    公开(公告)日:1994-05-03

    申请号:CA2039875

    申请日:1991-04-05

    Applicant: IBM

    Abstract: A process for forming the ridge structure of a self-aligned semiconductor laser, particularly useful for long wavelength devices as required for signal transmission systems. Described is the process as applied to an InP-system, double heterostructure (DH) laser. A thin Si3N4 layer (41) is inserted between the photoresist mask (42) that defines the ridge structure, and the contact layer (35). This results in improved adhesion and reduced etch undercutting whereby the ohmic contact area is increased, heat development decreased and device properties improved. Using a Si3N4 layer (41) deposited at a high plasma excitation frequency (RF) for adhesion promotion, and a low frequency deposited (LF) Si3N4 layer (43) for device embedding, provides for the etch selectivity required in the process stepthat is used to expose the contact layer to ohmic contact metallization deposition.

    METHOD FOR BATCH CLEAVING SEMICONDUCTOR WAFERS AND FOR COATING THE CLEAVED FACETS

    公开(公告)号:CA2043173C

    公开(公告)日:1993-09-21

    申请号:CA2043173

    申请日:1991-05-24

    Applicant: IBM

    Abstract: A method for cleaving semiconductor wafers, or segments thereof, which comprises placing the wafer (11), provided with scribe lines (15) defining the planes where cleaving is to take place, inbetween a pair of flexible transport bands (12, 13) and guiding it around a curved, large radius surface (21) therebyapplying a bending moment. With a moment of sufficient magnitude, individual bars (22) are broken off the wafer as this is advanced, the bars having frontand rear-end facets. On cleaving, each bar, while still pressed against the curved surface, is automatically separated whereby mutual damage of the facets of neighbouring bars is prevented. For further handling, e.g. for the transport of the bars to an evaporation station for passivation layer deposition, provisions are made to keep the bars separated. Cleaving and the subsequent passivation coating can be carried out in-situ in a vacuum system to prevent facet contamination prior to applying the passivation.

    INTEGRATED SEMICONDUCTOR DIODE LASER AND PHOTODIODE STRUCTURE

    公开(公告)号:CA2018502C

    公开(公告)日:1994-01-11

    申请号:CA2018502

    申请日:1990-06-07

    Applicant: IBM

    Abstract: Integrated semiconductor structure with optically coupled laser diode and photodiode, both devices having etched, vertical facets. The photodiode has a spatially non-uniform sensitivity profile with respect to the incident light beam emitted by the laser. This is due to the varying distance from the laser facet and/or to variations in the angle of incidence and results in photocurrents produced by the photodiode that depend on the intensity distribution of the light beam. The spatially non-uniform sensitivity profile allows the measurement of the far-field intensity distribution of the laser and thus on-wafer screening of lasers with respect to their mode-stability.

    PROCESS FOR FORMING THE RIDGE STRUCTURE OF A SELF-ALIGNED SEMICONDUCTOR LASER

    公开(公告)号:CA2039875A1

    公开(公告)日:1991-10-07

    申请号:CA2039875

    申请日:1991-04-05

    Applicant: IBM

    Abstract: A process for forming the ridge structure of a self-aligned semiconductor laser, particularly useful for long wavelength devices as required for signal transmission systems. Described is the process as applied to an InP-system, double heterostructure (DH) laser. A thin Si3N4 layer (41) is inserted between the photoresist mask (42) that defines the ridge structure, and the contact layer (35). This results in improved adhesion and reduced etch undercutting whereby the ohmic contact area is increased, heat development decreased and device properties improved. Using a Si3N4 layer (41) deposited at a high plasma excitation frequency (RF) for adhesion promotion, and a low frequency deposited (LF) Si3N4 layer (43) for device embedding, provides for the etch selectivity required in the process step that is used to expose the contact layer to ohmic contact metallization deposition.

    METHOD OF FABRICATING A SELF-ALIGNED METAL- SEMICONDUCTOR FET

    公开(公告)号:CA1266812A

    公开(公告)日:1990-03-20

    申请号:CA508352

    申请日:1986-05-05

    Applicant: IBM

    Abstract: Method of Fabricating a Self-Aligned Metal-Semiconductor FET A method for the fabrication of self-aligned MESFET structures (30) with a recessed refractory submicron gate. After channel formation (32) on a SI substrate (31), which may consist of a III-V compound semiconductor such as GaAs, with subsequent annealing the refractory gate (33G) is deposited and patterned. This is followed by the overgrowth of a highly doped contact layer of e.g. GaAs using MOCVD or MBE processes resulting in poly-cry-stalline material over the gate "mask" and in mono-cry-stalline material (34S, 34D) on exposed semiconductor surfaces. Next, the poly-crystalline material is removed in a selective etch process, this step being followed by the deposition of source and drain electrodes (35S, 35D). In order to further improve process reliability, insulating sidewalls (43-43) can be provided at the vertical edges of the gate (33G) to avoid source-gate and draingate shorts.

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