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    Method and apparatus for implementing memory access
    2.
    发明专利
    Method and apparatus for implementing memory access 审中-公开
    用于实现记忆访问的方法和装置

    公开(公告)号：JP2008102932A

    公开(公告)日：2008-05-01

    申请号：JP2007270106

    申请日：2007-10-17

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： VANDERWEIL STEVEN PAUL ,  TROMBLEY MICHAEL RAYMOND ,  M V V ANIL KRISHNA

    IPC: G06F12/02

    CPC classification number: G06F12/0215 ,  G06F13/1631

    Abstract: PROBLEM TO BE SOLVED: To provide a method and apparatus for implementing memory access to a memory using an open mode with data prefetching.
    SOLUTION: A central processor unit issues memory commands. A memory controller receiving the memory commands, identifies a data prefetching command. The memory controller checks whether a next sequential line for the identified prefetch command is within the page current being accessed, and responsive to identifying the next sequential line being within the current page, the current command is processed and the current page left open.
    COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种使用具有数据预取的开放模式来实现对存储器的存储器访问的方法和装置。 解决方案：中央处理器单元发出内存命令。 接收存储器命令的存储器控​​制器识别数据预取命令。 存储器控制器检查所识别的预取命令的下一个顺序行是否在被访问的页面当前中，并且响应于识别当前页面中的下一个顺序行，处理当前命令并且当前页面保持打开。 版权所有（C）2008，JPO＆INPIT

    SYSTEMS AND METHODS FOR MASKING LATENCY OF MEMORY REORGANIZATION WORK IN A COMPRESSED MEMORY SYSTEM
    3.
    发明申请
    SYSTEMS AND METHODS FOR MASKING LATENCY OF MEMORY REORGANIZATION WORK IN A COMPRESSED MEMORY SYSTEM 审中-公开
    用于掩蔽压缩存储器系统中存储器重组延迟的系统和方法

    公开(公告)号：WO2008030672A3

    公开(公告)日：2008-05-08

    申请号：PCT/US2007074721

    申请日：2007-07-30

    Applicant: IBM ,  DALY DAVID MICHAEL ,  FRANASZEK PETER ANTHONY ,  IGNATOWSKI MICHAEL ,  LASTRAS-MONTANO LUIS ALFONSO ,  TROMBLEY MICHAEL RAYMOND

    Inventor： DALY DAVID MICHAEL ,  FRANASZEK PETER ANTHONY ,  IGNATOWSKI MICHAEL ,  LASTRAS-MONTANO LUIS ALFONSO ,  TROMBLEY MICHAEL RAYMOND

    IPC: G06F12/08

    CPC classification number: G06F12/08 ,  G06F12/0804 ,  G06F12/1408 ,  G06F2212/401

    Abstract: Computer memory management systems and methods are provided hi which data block buffering and priority scheduling protocols are utilized in compressed memory systems to mask the latency associated with memory reorganization work following access to compressed main memory, to particular, data block buffers and priority scheduling protocols are implemented to delay and prioritize memory.reorganization work to allow resources to be used for serving new memory access requests and other high priority commands. In one aspect, a computer system ( 10) includes a main memory ( 160) comprising first (161) and second (162) memory' regions having different access characteristics, a memory controller (130) to manage the main memory (160) and to allow access to stored data items in the main memory (160), wherein the memory controller ( 130) implements a memory reorganization process comprising an execution flow of process steps for accessing a data hem that is stored in one of the first (161) or second memory region (162), and storing the accessed data item in the other one of the first (161) or second (162) memory region, and a local buffer memory (150) operated under control of the memory controller (130) to temporarily buffer data items to be written to the main memory (160) and data items read from the main memory (160) during the memory reorganization process, wherein the memory controller (130) temporarily suspends the execution flow of the memory reorganization process between process steps, if necessary, according to a priority schedule, and utilizes the local buffer memory (150) to temporarily store data that is to be processed when the memory reorganization process is resumed

    Abstract translation: 提供计算机存储器管理系统和方法，其中在压缩存储器系统中利用数据块缓冲和优先级调度协议来掩蔽与访问压缩主存储器之后的存储器重组工作相关的等待时间，特别是数据块缓冲器和优先级调度协议 实现延迟和优先化memory.reorganization工作，以允许资源用于服务新的内存访问请求和其他高优先级命令。 在一个方面中，一种计算机系统（10）包括：主存储器（160），其包括具有不同访问特性的第一存储区（161）和第二存储区（162）;管理主存储器（160）的存储器控​​制器（130）;以及 以允许访问主存储器（160）中存储的数据项，其中存储器控制器（130）实现存储器重组过程，该存储器重组过程包括用于访问存储在第一（161）中的一个中的数据卷边的处理步骤的执行流程， 或第二存储器区域（162）中，并且将访问的数据项存储在第一（161）或第二（162）存储器区域中的另一个中，以及在存储器控制器（130）的控制下操作的本地缓冲存储器（150） 在存储器重新组织过程期间临时缓存要写入主存储器（160）的数据项和从主存储器（160）读取的数据项，其中存储器控制器（130）暂时中止存储器重组过程的执行流程 过程步骤，i f根据优先级调度表，并且利用本地缓冲存储器（150）临时存储当恢复存储器重组过程时要处理的数据

    QUEUE MANAGER FOR A BUFFER
    5.
    发明专利
    QUEUE MANAGER FOR A BUFFER 未知

    公开(公告)号：CA2328268A1

    公开(公告)日：2001-07-04

    申请号：CA2328268

    申请日：2000-12-12

    Applicant: IBM

    Inventor： VERPLANKEN FABRICE JEAN ,  TROMBLEY MICHAEL RAYMOND ,  SIEGEL MICHAEL STEVEN ,  HEDDES MARCO C ,  CALVIGNAC JEAN LOUIS ,  BASS BRIAN MITCHELL

    IPC: G06F12/00 ,  G06F5/06 ,  G06F5/14 ,  G06F12/02 ,  G06F12/08 ,  G06F13/00 ,  G06F13/14 ,  G06F13/16 ,  G06F13/38

    Abstract: A bandwidth conserving queue manager for a FIFO buffer is provided, preferab ly on an ASIC chip and preferably including separate DRAM storage that maintains a FI FO queue which can extend beyond the data storage space of the FIFO buffer to provide additiona l data storage space as needed. FIFO buffers are used on the ASIC chip to store and retrieve multipl e queue entries. As long as the total size of the queue does not exceed the storage available in the buffers, no additional data storage is needed. However, when some predetermined amount of the buffe r storage space in the FIFO buffers is exceeded, data are written to and read from the addition al data storage, and preferably in packets which are of optimum size for maintaining peak performance of the data storage device and which are written to the data storage device in such a wa y that they are queued in a first-in, first-out (FIFO) sequence of addresses. Preferably, the data are written to and are read from the DRAM in burst mode.

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