公开(公告)号：JPH09117164A

公开(公告)日：1997-05-02

申请号：JP19877796

申请日：1996-07-29

Applicant: IBM

Inventor： KUROODO RUISU BAATEIN ,  JIYON EDOWAADO KUROONIN

IPC: B81B5/00 ,  B81B7/00 ,  B81C1/00 ,  B81C3/00 ,  H01H1/00 ,  H01L21/306 ,  H01L29/84 ,  H01L49/00 ,  H02N1/00

Abstract: PROBLEM TO BE SOLVED: To extensively apply the existing micromachine technology and thereby manufacture a machine which can perform a good job by forming a mechanical structure which includes a stack structure in which a plurality of layers are stacked and including movable member demarcated from a microstructure in at least one layer of the stack structure. SOLUTION: A pattern is formed on a substrate 12 using a mask and then a micromachine layer 10 is formed a microstructure constituted of a stator structure 16 and a rotor structure 18 which are demarcated by a hole 20 surrounding a hub 22 and a groove 14 is formed. The stator structures 16 and the rotor structures 18 are stacked to form an electrostatic motor of a stack structure constituted of a plurality of layers. By fabricating a machine by stacking, machines of micrometers, millimeters, and centimeters in size can be manufactured.

公开(公告)号：JPH09116000A

公开(公告)日：1997-05-02

申请号：JP23558196

申请日：1996-09-05

Applicant: IBM

Inventor： JIYON EDOWAADO KUROONIN

IPC: H01L21/60 ,  H01L21/768 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To prepare semiconductor structure containing a self-aligned stud-up formed of a single metallic layer and an interconnection wire efficiently by filling an opening section formed to an insulator region with a metal. SOLUTION: A stud-up 32 and an interconnection wire 34 connected to the stud-up 32 are contained, and the stud-up 32 and the interconnection wire 34 are self-aligned, and formed of a single metallic layer. When such semiconductor structure is prepared, an insulator region 11 is formed onto a semiconductor substrate, and the insulator region 11 is patterned and etched by using a mask 26 for demarcating an opening section 22A in beforehand selected depth. A metal is attached for filling the opening section 22A, and the interconnection wire 34 is formed by the attaching of the metal. The stud-up 32 in desired size is patterned and formed so that the lower end of the stud-up 32 is connected to the interconnection wire 34 and the upper end of the stud-up 32 is terminated on the top face of the insulator region 11 or a section in the vicinity of the top face in the metal-filled opening section.

公开(公告)号：JPH08204117A

公开(公告)日：1996-08-09

申请号：JP26817395

申请日：1995-10-17

Applicant: IBM

Inventor： JIYON EDOWAADO KUROONIN ,  SUCHIIBUN ERINUTSUDO RUUSU ,  SUCHIIBUN HAWAADO BUORUDOMAN

IPC: H01L25/00 ,  H01L21/98 ,  H01L25/065 ,  H01L25/07 ,  H01L25/16 ,  H01L25/18

Abstract: PROBLEM TO BE SOLVED: To obtain an electronic module enhanced with interconnects and components, by collectively forming electronic components containing an electronic module, on an almost flat surface of the electronic module which has a plurality of stacked integrated circuit chips and the almost flat surface. SOLUTION: Chips 11 are stacked and an electronic module is formed, and transfer metal 17 is followed. After the chips are laminated, a flat surface is formed by etching the side surface of the module. Positions of interconnects are specified, a mask is formed, etching is performed, a notch is formed, and insulator and further conductor are buried in the notch, thereby forming interconnects 19a, 19b which are electrically insulated from a board. The surfaces 23, 24 of the module where the interconnects intersect with each other are polished, and the surfaces are flattened. The side surfaces of the module are metallized, and the chips are interconnected.

公开(公告)号：JPH08191047A

公开(公告)日：1996-07-23

申请号：JP20311595

申请日：1995-08-09

Applicant: IBM

Inventor： JIYON EDOWAADO KUROONIN ,  DEEBUITSUDO CHIYAARUZU TOMASU ,  EDOWAADO DANIERU BIYUUKAA ,  KURISUTEIIN AN ANDAASON ,  GUROORIA JIIN KERUSHIYUKOFUSUK

IPC: H01L21/027 ,  H01L21/316 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To obtain a highly accurate method for metallization by forming a dielectric layer and a titanium nitride layer on a substrate and patterning both layers before titanium nitride and a metal adhere thereto. SOLUTION: A semiconductor, typical in the processing stage, is provided on a substrate 20 and a dielectric layer 32 is formed thereon before planalization takes place. It is then coated with antireflection titanium nitride 34 and both layers 32, 34 are patterned to make an opening. Subsequently, a second titanium nitride layer 44 are formed on the titanium nitride layer 34 and the via or channel. The trench is then filled up and a metal layer 46 of W, for example, is formed while extending onto the titanium nitride layer 44. Consequently, a highly accurate method for metallization is obtained as well as an antireflection film coated directly with a metal and adhesion of metal and dielectric is improved in the dielectric layer.

公开(公告)号：JPH0613583A

公开(公告)日：1994-01-21

申请号：JP3189093

申请日：1993-02-22

Applicant: IBM

Inventor： ARUBAATO SUTEIIBUN BERUGENDAAR ,  KUROODO RUI BERUTAN ,  JIYON EDOWAADO KUROONIN ,  HAWAADO REO KARUTAA ,  DONARUDO MAKARUPAIN KENII ,  CHIYUN HON RAMU ,  SHIN SAN RII

IPC: H01L27/10 ,  H01L21/8239 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE: To provide a shadow RAM, which occupies only 120% or less of the space of only a DRAM by using an EEPROM in a trench in the array of the DRAM. CONSTITUTION: A memory capacitor 3 of the deep trench of polysilicon is arranged between a word line 1 and a bit line, where its contact 2 is shown. An insulating region 4 of a shallow trench is located between a pair of the deep-trench memory capacitors 3 neighboring the contact 2 and blocks stray surface currents. An EEPROM trench includes a series of discontinuous polysilicon floating gates 5, a continuous polysilicon recall-gate extending part 6, a continuous polysilicon program gate, a silicon oxide layer 8 for insulation and a dielectric spacer 7 having abundant silicon between the floating gate 5 and the recall-gate extending part 6, and between the floating gate and the program gate.

公开(公告)号：JPS6475691A

公开(公告)日：1989-03-22

申请号：JP14843888

申请日：1988-06-17

Applicant: IBM

Inventor： ROBAATO KUROUERU BAASUMISU ,  UIRIAMU JIYOSEFU KOTE ,  JIYON EDOWAADO KUROONIN ,  KAREI REN HOORANDO ,  KAATAA UERINGU KANTA ,  PEIIINGU POORU RII ,  TERANSU MONTE RAITO

IPC: C23F4/00 ,  H01L21/3213

公开(公告)号：JPH06342206A

公开(公告)日：1994-12-13

申请号：JP23381091

申请日：1991-08-22

Applicant: IBM

Inventor： JIYON EDOWAADO KUROONIN ,  POORU OORUDEN FUARAA SHINIA ,  KAATAA UERINGU KAANTA ,  JIEEMUZU GAADONAA RIYAN ,  ANDORIYUU JIYOSEFU WATSUTSU

IPC: G03F1/00 ,  G03F7/00 ,  G03F9/00 ,  H01L21/027 ,  G03F1/08

Abstract: PURPOSE: To provide a gray level mask suitable for photolithoigraphy which consists of a transparent glass substrate bearing materials of plural levels having different optical transmittasbilities. CONSTITUTION: In the case of a mask using two levels alone, the first layer 24A thereof may be composed of glass formed to partially have transmittability by execution of substitution of silver ions in place of the metal ions of an alkaline metal silicate used in production of glass. The second layer 24B thereof may be formed opaque by constituting the layer of a metallic layer, such as chromium. The mask is constituted by the assistance of a photoresist constituting body 26 etched by a photolithographical masking operation in the specific regions in order to enable the selective etching operation with respect to the exposed regions of the materials of the levels having the different optical transmittabilies.

公开(公告)号：JPH0669199A

公开(公告)日：1994-03-11

申请号：JP7730791

申请日：1991-03-18

Applicant: IBM

Inventor： JIYON EDOWAADO KUROONIN ,  KAATAA UERINGU KAANTA

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52

Abstract: PURPOSE: To improve the capability of ensuring self-alignment of multi-stage interconnection metalization by providing three-stage self-alignment metalization. CONSTITUTION: A subsequent mask 28 of defining an interconnection via and a second stage interconnection uses at least one edge of a first mask pattern as a common element for defining the subsequent metal mask. Overlaying of the mask is avoided by combining an etching stop layer 14 and an oversized second stage mask. As a result, it is unnecessary to consider a positioning error of the mask upon formation of a metalization via, by employing a common vertical edge or common flat surface, defined by the first mask which defines the first stage interconnection.

公开(公告)号：JPH0615770A

公开(公告)日：1994-01-25

申请号：JP25563691

申请日：1991-10-03

Applicant: IBM

Inventor： JIYON EDOWAADO KUROONIN ,  POORU OORUDEN FUARAA SHIINIA ,  HARORUDO JIYOOJI RINDE ,  ROOZUMARII AN PUREBITEIIKERII

IPC: B32B7/04 ,  B32B15/08 ,  B32B15/088 ,  B32B37/00 ,  C08G73/10 ,  C08J5/12 ,  C09D4/00 ,  C09D183/04 ,  C09D183/08 ,  G03F7/075 ,  G03F7/09 ,  H01L21/312 ,  H05K3/28 ,  B32B31/00

Abstract: PURPOSE: To improve humidity resistance, to enhance the resistance to the oxidation of a metal and to obtain heat stability by applying a soln. comprising a polyimide precursor material to a cured layer and heating a substrate so as to imidate the polyimide precursor material. CONSTITUTION: An org. soln. prepared by reacting an aminoalkoxysilane monomer and water in a solvent within a range of about 1:1-1.7:1 is applied to a metal substrate at first. This substrate is heated so as to form a layer of a cured silsesquioxane polymer and a metal is passivated to suppress the interaction between a metal and a polyimide precursor material to be coated. Subsequently, a soln. of the polyimide precursor material is applied to the metal substrate and this metal substrate is again heated in order to imidate the polyimide precursor material. By this operation, an effective passivated layer is formed and humidity resistance, oxidation resistance and high heat stability can be achieved.

公开(公告)号：JPH04229638A

公开(公告)日：1992-08-19

申请号：JP8934391

申请日：1991-03-29

Applicant: IBM

Inventor： JIYON EDOWAADO KUROONIN ,  KAATAA UERINGU KAANTA ,  ROOZUMARII AN PUREBITEIIKERII ,  JIEIMUZU GAADONAA RAIAN

IPC: C08L79/08 ,  H01L21/312 ,  H01L21/768 ,  H01L23/528

Abstract: PURPOSE: To provide a method for manufacturing the multi-level coplanar conductor/insulator film on a machined semiconductor base with a conductor pattern. CONSTITUTION: A development stop layer is given to a 1st layer, and a 2nd layer formed of a photosensitive polyimide polymer composition is given to the development stop layer. The 2nd layer is exposed to an image so that part of the development stop layer is selectively exposed, and then developed, and the exposed part is removed. The 1st layer is exposed to an image, so that the region of the base is selectively exposed, and then developed (here, an opening part formed in the 1st layer is matched with at least part of an opening part formed in the 2nd layer). A conductor substance is deposited on the 2nd layer and in the openings in the 1st and 2nd layers, and the conductor substance laid on the 2nd layer is removed to form the surface of the conductor substance to be flush with the 2nd layer.