公开(公告)号：SG101957A1

公开(公告)日：2004-02-27

申请号：SG200100731

申请日：2001-02-10

Applicant: IBM

Inventor： CHARLES R DAVIS ,  DANIEL CHARLES EDELSTEIN ,  JOHN C HAY ,  JEFFREY C HENDRICK ,  CHRISTOPHER JAHNES ,  VINCENT J MCGAHAY

IPC: H01L21/768 ,  H01L21/3205 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532

Abstract: A multi-level, coplanar copper damascene interconnect structure on an integrated circuit chip includes a first planar interconnect layer on an integrated circuit substrate and having plural line conductors separated by a dielectric material having a relatively low dielectric constant and a relatively low elastic modulus. A second planar interconnect layer on the first planar interconnect layer comprises a dielectric film having an elastic modulus higher than in the first planar interconnect layer and conductive vias therethrough. The vias are selectively in contact with the line conductors. A third planar interconnect layer on the second planar interconnect layer has plural line conductors separated by the dielectric material and selectively in contact with the vias.