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公开(公告)号:SG96261A1
公开(公告)日:2003-05-23
申请号:SG200107065
申请日:2001-11-13
Applicant: IBM
Inventor: KEVIN PETRARCA , ROBERT A GROVES , BRIAN HERBST , CHRISTOPHER JAHNES , RICHARD VOLANT
Abstract: A micro electromechanical switch has a guidepost formed upon a substrate. A signal transmission line is formed on the substrate, with the signal transmission line having a gap and forming an open circuit. The switch further includes a switch body having a via opening formed therein, with the switch body being movably disposed along an length defined by the guide post. The guidepost is partially surrounded by the via opening.
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公开(公告)号:SG115320A1
公开(公告)日:2005-10-28
申请号:SG1998001197
申请日:1998-06-04
Applicant: IBM
Inventor: KATHERINA E BABICH , ALESSANDRO CESARE CALLEGARI , JULIEN FONTAINE , ALFRED GRILL , CHRISTOPHER JAHNES , VISHNUBHAI VITTHALBHAI PATEL
IPC: H01L21/3205 , C23C16/26 , C23C16/30 , G03F7/09 , H01L21/027 , H01L21/311 , H01L21/312
Abstract: Disclosed is vapor deposited BARC and method of preparing tunable and removable antireflective coatings based on amorphous carbon films. These films can be hydrogenated, fluorinated, nitrogenated carbon films. Such films have an index of refraction and an extinction coefficient tunable from about 1.4 to about 2.1 and from about 0.1 to about 0.6, respectively, at UV and DUV wavelengths, in particular 365, 248 and 193 nm. Moreover, the films produced by the present invention can be deposited over device topography with high conformality, and they are etchable by oxygen and/or a fluoride ion etch process. Because of their unique properties, these films can be used to form a tunable and removable antireflective coating at UV and DUV wavelengths to produce near zero reflectance at the resist/BARC coating interface. This BARC greatly improves performance of semiconductor chips.
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公开(公告)号:SG101957A1
公开(公告)日:2004-02-27
申请号:SG200100731
申请日:2001-02-10
Applicant: IBM
Inventor: CHARLES R DAVIS , DANIEL CHARLES EDELSTEIN , JOHN C HAY , JEFFREY C HENDRICK , CHRISTOPHER JAHNES , VINCENT J MCGAHAY
IPC: H01L21/768 , H01L21/3205 , H01L23/52 , H01L23/522 , H01L23/532
Abstract: A multi-level, coplanar copper damascene interconnect structure on an integrated circuit chip includes a first planar interconnect layer on an integrated circuit substrate and having plural line conductors separated by a dielectric material having a relatively low dielectric constant and a relatively low elastic modulus. A second planar interconnect layer on the first planar interconnect layer comprises a dielectric film having an elastic modulus higher than in the first planar interconnect layer and conductive vias therethrough. The vias are selectively in contact with the line conductors. A third planar interconnect layer on the second planar interconnect layer has plural line conductors separated by the dielectric material and selectively in contact with the vias.
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公开(公告)号:SG102613A1
公开(公告)日:2004-03-26
申请号:SG200100695
申请日:2001-02-08
Applicant: IBM
Inventor: JUDITH M RUBINO , CHRISTOPHER JAHNES , ERIC G LINIGER , JAMES GARDNER RYAN , CARLOS J SAMBUCETTI , FRANK CARDONE , SAMPATH PURUSHOTHAMAN , JOHN ANTHONY FITZSIMMONS , STEPHEN MCCONNELL GATES
IPC: C22F1/10 , C22C19/00 , C22F1/00 , H01L21/28 , H01L21/31 , H01L21/314 , H01L21/316 , H01L21/3205 , H01L21/324 , H01L21/76 , H01L21/768 , H01L23/52 , H01L23/522 , H01L23/532
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