公开(公告)号：JP2003347233A

公开(公告)日：2003-12-05

申请号：JP2003132210

申请日：2003-05-09

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： GEISS PETER J ,  JOSEPH R GRECO ,  KONTRA RICHARD S ,  LANNING EMILY

IPC: H01L21/28 ,  H01L21/20 ,  H01L21/265 ,  H01L21/331 ,  H01L21/822 ,  H01L27/04 ,  H01L29/08 ,  H01L29/49 ,  H01L29/732 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2652 ,  H01L29/0804 ,  H01L29/1083 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/66242 ,  H01L29/7375 ,  H01L29/7378 ,  Y10S257/914

Abstract: PROBLEM TO BE SOLVED: To provide a method of adjusting a particle size in a polysilicon layer, and to provide a device manufactured by the method.
SOLUTION: In the method, the polysilicon layer is formed on a substrate and the particle size in the polysilicon layer is adjusted so that the average resulting particle size of the polysilicon layer after a polysilicon particle-size adjusting ion is injected into the layer and prescribed annealing is performed on the layer becomes higher or lower than an average resulting particle-size that must be obtained after the same annealing is performed on the polysilicon layer without injecting the ion into the layer by injecting the particle-size adjusting ion into the polysilicon layer.
COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：提供一种调整多晶硅层中的粒径的方法，并提供通过该方法制造的器件。 解决方案：在该方法中，在衬底上形成多晶硅层，并调节多晶硅层中的粒径，使多晶硅粒度调整离子后的多晶硅层的平均粒径注入到 在层上进行规定的退火，高于或低于在多晶硅层上进行相同的退火之后必须获得的平均粒子尺寸，而不通过将粒径调节离子注入到层中而将离子注入层中 多晶硅层。 版权所有（C）2004，JPO

公开(公告)号：JP2000228405A

公开(公告)日：2000-08-15

申请号：JP2000023868

申请日：2000-02-01

Applicant: IBM

Inventor： ARNE W BALLANTINE ,  DOUGLAS D KUURUBOU ,  JEFFREY GILBERT ,  JOSEPH R GRECO ,  GLENN R MILLER

IPC: H01L29/73 ,  H01L21/314 ,  H01L21/318 ,  H01L21/328 ,  H01L21/331 ,  H01L29/08

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming, at least, one interface region between two semiconductor material regions. SOLUTION: Dielectric regions 9 are partially formed at an interface 5 between a single crystal silicon 1 and a polycrystalline silicon 3. The dielectric regions 9 are formed by injecting nitrogen atoms into the single crystal silicon 1. The formed dielectric regions 9 have thickness of 1 to 10 Å. A dielectric layer is provided at an interface between two silicons by the use of nitrogen, by which each wafer can be controlled in electric resistance at an interface. In an NPN transistor, a dielectric layer is formed between an emitter and a contact, by which a base current and a current gain β can be controlled.