公开(公告)号：EP1905074A4

公开(公告)日：2012-06-27

申请号：EP06773946

申请日：2006-06-26

Applicant: IBM

Inventor： BRYANT ANDRES ,  NOWAK EDWARD J ,  WILLIAMS RICHARD Q

IPC: H01L21/84 ,  H01L27/108 ,  H01L29/786

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/0811 ,  H01L28/40 ,  H01L29/78648 ,  Y10T436/235 ,  Y10T436/25125 ,  Y10T436/2525 ,  Y10T436/25375

公开(公告)号：EP1910954A4

公开(公告)日：2012-04-11

申请号：EP06800366

申请日：2006-07-26

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  JORDAN DONALD L ,  MCCULLEN JUDITH H ,  ONSONGO DAVID M ,  WAGNER TINA ,  WILLIAMS RICHARD Q

IPC: G06F7/48 ,  G06F17/50

CPC classification number: G06F17/5068 ,  G06F17/5036 ,  H01L29/7843

公开(公告)号：EP1652235A4

公开(公告)日：2008-09-17

申请号：EP04757122

申请日：2004-07-19

Applicant: IBM

Inventor： JOSHI RAJIV V ,  WILLIAMS RICHARD Q

IPC: H01L29/786 ,  H01L20060101 ,  H01L21/336 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/01 ,  H01L27/11 ,  H01L27/12 ,  H01L29/06 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC classification number: H01L29/785 ,  H01L21/84 ,  H01L21/845 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203 ,  H01L27/1207 ,  H01L27/1211 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/78687 ,  Y10S257/903

Abstract: A channel (16) of a FinFET (10) has a channel core (24) and a channel envelope (32), each made from a semiconductor material defining a different lattice structure to exploit strained silicon properties. A gate is coupled to the channel envelope through a gate dielectric. Exemplary materials are Si and SixGe1-x, wherein 78

公开(公告)号：JP2003208456A

公开(公告)日：2003-07-25

申请号：JP2002365608

申请日：2002-12-17

Applicant: IBM

Inventor： KERRY BERNSTEIN ,  WATTS JOSEF S ,  WILLIAMS RICHARD Q

IPC: G06F17/50

Abstract: PROBLEM TO BE SOLVED: To provide a method and structure for a computer model for a device having a performance parameter. SOLUTION: A first bounded range and a second bounded range are included in the performance parameter. The first bounded range has performance parameter fluctuation within a single production process, and the second bounded range has performance parameter fluctuation in different device design. COPYRIGHT: (C)2003,JPO

公开(公告)号：WO2007016183A3

公开(公告)日：2008-12-18

申请号：PCT/US2006029069

申请日：2006-07-26

Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  JORDAN DONALD L ,  MCCULLEN JUDITH H ,  ONSONGO DAVID M ,  WAGNER TINA ,  WILLIAMS RICHARD Q

Inventor： CHIDAMBARRAO DURESETI ,  JORDAN DONALD L ,  MCCULLEN JUDITH H ,  ONSONGO DAVID M ,  WAGNER TINA ,  WILLIAMS RICHARD Q

IPC: G06F7/48

CPC classification number: G06F17/5068 ,  G06F17/5036 ,  H01L29/7843

Abstract: System and method for compact model algorithms (310-350) to accurately account for effects of layout-induced changes in nitride liner (260) stress in semiconductor devices (200). The layout- sensitive compact model algorithms (310-350) account for the impact of large layout variation on circuits by implementing algorithms for obtaining the correct stress response approximations and layout extraction algorithms for obtaining the correct geometric parameters that drive the stress response. In particular, these algorithms include specific information from search "buckets" that are directionally-oriented and include directionally-specific distance measurements for analyzing in detail the specific shape neighborhood of the semiconductor device. The algorithms are additionally adapted to enable the modeling and stress impact determination of a device having single stress liner film and dual-stress liners (260) (two different liner films that abut at an interface).

Abstract translation: 用于紧凑模型算法（310-350）的系统和方法来准确地说明半导体器件（200）中氮化物衬垫（260）应力的布局引起的变化的影响。 布局敏感的紧凑模型算法（310-350）通过实现用于获得正确的应力响应近似和布局提取算法的算法来解决大布局变化对电路的影响，以获得驱动应力响应的正确几何参数。 特别地，这些算法包括来自定向定向的搜索“桶”的特定信息，并且包括用于详细分析半导体器件的特定形状邻域的定向特定的距离测量。 这些算法还适用于能够确定具有单个应力衬垫膜和双应力衬垫（260）（在界面处邻接的两个不同衬垫膜）的器件的建模和应力冲击测定。

公开(公告)号：WO2005010944A3

公开(公告)日：2005-08-11

申请号：PCT/US2004023183

申请日：2004-07-19

Applicant: IBM ,  JOSHI RAJIV V ,  WILLIAMS RICHARD Q

Inventor： JOSHI RAJIV V ,  WILLIAMS RICHARD Q

IPC: H01L20060101 ,  H01L21/336 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/01 ,  H01L27/11 ,  H01L27/12 ,  H01L29/06 ,  H01L29/786 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC classification number: H01L29/785 ,  H01L21/84 ,  H01L21/845 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203 ,  H01L27/1207 ,  H01L27/1211 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/78687 ,  Y10S257/903

Abstract: A channel (16) of a FinFET (10) has a channel core (24) and a channel envelope (32), each made from a semiconductor material defining a different lattice structure to exploit strained silicon properties. A gate is coupled to the channel envelope through a gate dielectric. Exemplary materials are Si and SixGe1-x, wherein 78

Abstract translation: FinFET（10）的沟道（16）具有沟道芯（24）和沟道包络（32），每个沟道包络由限定不同晶格结构的半导体材料制成以利用应变硅特性。 栅极通过栅极电介质耦合到沟道外壳。 示例性的材料是Si和SixGe1-x，其中78

公开(公告)号：WO2007011496A3

公开(公告)日：2008-05-29

申请号：PCT/US2006024701

申请日：2006-06-26

Applicant: IBM ,  BRYANT ANDRES ,  NOWAK EDWARD J ,  WILLIAMS RICHARD Q

Inventor： BRYANT ANDRES ,  NOWAK EDWARD J ,  WILLIAMS RICHARD Q

IPC: H01L21/84 ,  H01L27/108

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/0811 ,  H01L28/40 ,  H01L29/78648 ,  Y10T436/235 ,  Y10T436/25125 ,  Y10T436/2525 ,  Y10T436/25375

Abstract: A method of manufacture and device for a dual-gate CMOS structure. The structure includes a first plate (106a-d) in an insulating layer (100) and a second plate (110a-d) above the insulating layer electrically corresponding to the first plate. An isolation structure (108a-d) is between the first plate and the second plate.

Abstract translation: 一种双栅极CMOS结构的制造方法和器件。 该结构包括绝缘层（100）中的第一板（106a-d）和与第一板电对应的绝缘层上方的第二板（110a-d）。 隔离结构（108a-d）位于第一板和第二板之间。