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    Back-side memory element with local memory select transistor
    1.
    发明专利
    Back-side memory element with local memory select transistor 未知

    公开(公告)号：GB2579729B

    公开(公告)日：2022-06-08

    申请号：GB202001670

    申请日：2018-07-18

    Applicant: IBM

    Inventor： JOSHUA RUBIN ,  ARVIND KUMAR

    IPC: H01L27/22 ,  H01L43/12

    Abstract: A memory device includes a semiconductor device on a wafer. The semiconductor device includes a gate structure, a first source/drain region, and a second source/drain region. The gate structure is on the first side of the wafer. The first source/drain region is also on the first side of the wafer, and contacts a first end of the gate structure. The second source/drain region is on the second side of the wafer and extends into the first side to contact a second end of the gate structure. The memory device further includes a memory storage element on the second side of the wafer. The memory storage element contacts the second source/drain region.

    Secure chip identification using resistive processing unit as a physically unclonable function
    2.
    发明专利
    Secure chip identification using resistive processing unit as a physically unclonable function 未知

    公开(公告)号：IL296249A

    公开(公告)日：2022-11-01

    申请号：IL29624922

    申请日：2022-09-06

    Applicant: IBM ,  ARVIND KUMAR ,  TAKASHI ANDO ,  DIRK PFEIFFER

    Inventor： ARVIND KUMAR ,  TAKASHI ANDO ,  DIRK PFEIFFER

    IPC: G06F21/73 ,  G06F21/75 ,  G06F21/78 ,  G11C13/00 ,  G11C29/44 ,  G11C29/50

    Abstract: A technique relates to biasing, using a control system, a crossbar array of resistive processing units (RPUs) under a midrange condition, the midrange condition causing resistances of the RPUs to result in a random output of low values and high values in about equal proportions. The control system reinforces the low values and the high values of the random output by setting the resistances of the RPUs to a state that forces the low values and the high values having resulted from the midrange condition. Reinforcing the low values and the high values makes the random output permanent even when the crossbar array of the RPUs is not biased under the midrange condition. The control system records a sequence of the low values and the high values of the random output responsive to reinforcing the low values and the high values of the random output.

    Secure chip identification using resistive processing unit as a physically unclonable function
    3.
    发明专利
    Secure chip identification using resistive processing unit as a physically unclonable function 未知

    公开(公告)号：GB2610344B

    公开(公告)日：2025-01-15

    申请号：GB202217559

    申请日：2021-03-19

    Applicant: IBM

    Inventor： ARVIND KUMAR ,  TASASHI ANDO ,  DIRK PFEIFFER

    IPC: G11C13/00 ,  G06F21/73 ,  G11C8/20 ,  H04L9/32

    Abstract: A technique relates to biasing, using a control system, a crossbar array of resistive processing units (RPUs) under a midrange condition, the midrange condition causing resistances of the RPUs to result in a random output of low values and high values in about equal proportions. The control system reinforces the low values and the high values of the random output by setting the resistances of the RPUs to a state that forces the low values and the high values having resulted from the midrange condition. Reinforcing the low values and the high values makes the random output permanent even when the crossbar array of the RPUs is not biased under the midrange condition. The control system records a sequence of the low values and the high values of the random output responsive to reinforcing the low values and the high values of the random output.

    Heterogeneous integration structure for artificial intelligence computing
    4.
    发明专利
    Heterogeneous integration structure for artificial intelligence computing 未知

    公开(公告)号：GB2600585B

    公开(公告)日：2024-03-27

    申请号：GB202200773

    申请日：2020-06-16

    Applicant: IBM

    Inventor： MUKTA FAROOQ ,  ARVIND KUMAR

    IPC: H01L25/065 ,  G06F15/78 ,  H01L25/18

    Abstract: Three-dimensional (3D) semiconductor memory structures and methods of forming 3D semiconductor memory structures are provided. The 3D semiconductor memory structure includes a chip comprising a memory and Through-Silicon Vias (TSVs). The 3D semiconductor memory structure further includes a hardware accelerator arranged on and coupled face-to-face to the above chip. The 3D semiconductor memory structure also includes a substrate arranged under the under the (3D) semiconductor memory structure and the hardware accelerator and attached to the TSVs and external inputs and outputs of the memory chip and the hardware accelerator.

    Visual object and event detection and prediction system using saccades
    5.
    发明专利
    Visual object and event detection and prediction system using saccades 未知

    公开(公告)号：GB2547752A

    公开(公告)日：2017-08-30

    申请号：GB201621726

    申请日：2016-12-20

    Applicant: IBM

    Inventor： SHARATHCHANDRA UMAPATHIRAO PANKANTI ,  ARVIND KUMAR ,  JANUSZ MARECKI ,  BAN KAWAS

    IPC: G06T7/70

    Abstract: A received image (1301) is divided into patches, which may have different sizes. A cluster-direction sequence (see fig. 6) is generated (1302) for each of a plurality of saccadic paths along the patches, the paths being given by a policy matrix (see figs. 8 & 9). The sequences are used to identify an object in the image. Path sequence generation using the matrix may comprise assigning (1303) a likelihood (which may be weighted (1304) using a total frequency of occurrence of the sequence in the matrix for a given class) that the image belongs to each class defined in the matrix, and identifying (1305) the object using a likelihood average over the sequences. Image context, e.g. previous observations or goal, may be used. The patches may be clustered into groups, e.g. using k-means clustering algorithm (see figs. 4&5). Specific salient features in an image may thus be identified, leading to a classification of the image by judging whether the salient features can identify a unique class of object (e.g. 9 MNIST digits, or image classes in ImageNet, e.g. cats, planes etc.) in the image with high probability. Classification may occur through progressive exclusion of other classes.

    Heterogeneous integration structure for artificial intelligence computing
    6.
    发明专利
    Heterogeneous integration structure for artificial intelligence computing 未知

    公开(公告)号：GB2600585A

    公开(公告)日：2022-05-04

    申请号：GB202200773

    申请日：2020-06-16

    Applicant: IBM

    Inventor： MUKTA FAROOQ ,  ARVIND KUMAR

    IPC: G06F15/78

    Abstract: Three-dimensional (3D) semiconductor memory structures and methods of forming 3D semiconductor memory structures are provided. The 3D semiconductor memory structure includes a chip comprising a memory and Through-Silicon Vias (TSVs). The 3D semiconductor memory structure further includes a hardware accelerator arranged on and coupled face-to-face to the above chip. The 3D semiconductor memory structure also includes a substrate arranged under the under the (3D) semiconductor memory structure and the hardware accelerator and attached to the TSVs and external inputs and outputs of the memory chip and the hardware accelerator.

    Back-side memory element with local memory select transistor
    7.
    发明专利
    Back-side memory element with local memory select transistor 未知

    公开(公告)号：GB2579729A

    公开(公告)日：2020-07-01

    申请号：GB202001670

    申请日：2018-07-18

    Applicant: IBM

    Inventor： JOSHUA RUBIN ,  ARVIND KUMAR

    IPC: H01L27/22 ,  H01L43/12

    Abstract: A memory device includes a semiconductor device on a wafer. The semiconductor device includes a gate structure, a first source/drain region, and a second source/drain region. The gate structure is on the first side of the wafer. The first source/drain region is also on the first side of the wafer, and contacts a first end of the gate structure. The second source/drain region is on the second side of the wafer and extends into the first side to contact a second end of the gate structure. The memory device further includes a memory storage element on the second side of the wafer. The memory storage element contacts the second source/drain region.

    Secure chip identification using resistive processing unit as a physically unclonable function
    8.
    发明专利
    Secure chip identification using resistive processing unit as a physically unclonable function 未知

    公开(公告)号：IL296249B1

    公开(公告)日：2025-04-01

    申请号：IL29624922

    申请日：2022-09-06

    Applicant: IBM ,  ARVIND KUMAR ,  TAKASHI ANDO ,  DIRK PFEIFFER

    Inventor： ARVIND KUMAR ,  TAKASHI ANDO ,  DIRK PFEIFFER

    IPC: G06F21/73 ,  G06F21/75 ,  G06F21/78 ,  G11C13/00 ,  G11C29/44 ,  G11C29/50

    Abstract: A technique relates to biasing, using a control system, a crossbar array of resistive processing units (RPUs) under a midrange condition, the midrange condition causing resistances of the RPUs to result in a random output of low values and high values in about equal proportions. The control system reinforces the low values and the high values of the random output by setting the resistances of the RPUs to a state that forces the low values and the high values having resulted from the midrange condition. Reinforcing the low values and the high values makes the random output permanent even when the crossbar array of the RPUs is not biased under the midrange condition. The control system records a sequence of the low values and the high values of the random output responsive to reinforcing the low values and the high values of the random output.

    Visual Object and Event Detection and Prediction System using Saccades
    9.
    发明专利
    Visual Object and Event Detection and Prediction System using Saccades 未知

    公开(公告)号：GB2547752B

    公开(公告)日：2018-01-24

    申请号：GB201621726

    申请日：2016-12-20

    Applicant: IBM

    Inventor： SHARATHCHANDRA UMAPATHIRAO PANKANTI ,  ARVIND KUMAR ,  JANUSZ MARECKI ,  BAN KAWAS

    IPC: G06T7/70

    Abstract: A method of operating an image detection device includes receiving an image, dividing the image into a plurality of patches, grouping ones of the plurality of patches, generating a set of saccadic paths through the plurality of patches of the image, generating a cluster-direction sequence for each saccadic path, generating a policy function for identifying an object in a new image using a combination of the cluster-direction sequences, and operating the image detection device using the policy function to identify an object in the new image.

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