公开(公告)号：CA1063251A

公开(公告)日：1979-09-25

申请号：CA312408

申请日：1978-09-29

Applicant: IBM

Inventor： JOY RICHARD C ,  MAGDO INGRID E ,  PHILLIPS ALFRED JR

IPC: H01L29/78

Abstract: FIELD EFFECT TRANSISTOR HAVING IMPROVED THRESHOLD STABILITY An improved field effect transistor device in a monocrystalline semiconductor body provided with source and drain regions and a gate electrode disposed over the channel between the source and drain regions wherein at least the drain region is formed of a first region where the impurity concentration increases with depth with the peak concentration being spaced inwardly from the major surface, and a second region located within the first region having a peak impurity concentration at the major surface. The drain region structure in operation promotes the current flow between the source and drain to flow deeper in the channel region and spaced from the gate dielectric layer. In the method for forming the field effect transistor, an impurity is introduced into the semiconductor body underlying at least the ultimate drain region, an epitaxial semiconductor layer deposited, and a second impurity region formed over the first region to form the drain contact. In an alternate embodiment of the method for forming a field effect transistor, a first ion implantation is formed in the drain region, such that the peak impurity concentration is located well within the body spaced from the surface thereof, and a second ion implantation, or diffusion, performed forming the source and also the ohmic contact for the drain which is located over the first region and within the first implanted region.

公开(公告)号：CA1049154A

公开(公告)日：1979-02-20

申请号：CA261431

申请日：1976-09-17

Applicant: IBM

Inventor： JOY RICHARD C ,  MAGDO INGRID E ,  PHILLIPS ALFRED JR

IPC: H01L21/331 ,  H01L29/73 ,  H01L29/78

Abstract: FIELD EFFECT TRANSISTOR HAVING IMPROVED THRESHOLD STABILITY An improved field effect transistor device in a monocrystalline semiconductor body provided with source and drain regions and a gate electrode disposed over the channel between the source and drain regions wherein at least the drain region is formed of a first region where the impurity concentration increases with depth with the peak concentration being spaced inwardly from the major surface, and a second region located within the first region having a peak impurity concentration at the major surface. The drain region structure in operation promotes the current flow between the source and drain to flow deeper in the channel region and spaced from the gate dielectric layer. In the method for forming the field effect transistor, an impurity is introduced into the semi.conductor body underlying at least the ultimate drain region, an epitaxial semiconductor layer deposited, and a second impurity region formed over the first region to form the drain contact. In an alternate embodiment of the method for forming a field effect transistor, a first ion implantation is formed in the drain region, such that the peak impurity concentration is located well within the body spaced from the surface thereof, and a second ion implantation, or diffusion, performed forming the source and also the ohmic contact for the drain which is located over the first region and within the first implanted region.

公开(公告)号：CA1048653A

公开(公告)日：1979-02-13

申请号：CA258550

申请日：1976-08-06

Applicant: IBM

Inventor： BURR PETER ,  JOY RICHARD C ,  ZIEGLER JAMES F

IPC: H01L27/08 ,  H01L21/265 ,  H01L21/322 ,  H01L21/331 ,  H01L21/76 ,  H01L21/8222 ,  H01L27/06 ,  H01L27/092 ,  H01L29/08 ,  H01L29/167 ,  H01L29/73 ,  H01L29/78

Abstract: METHOD AND STRUCTURE FOR CONTROLLING CARRIER LIFETIME IN SEMICONDUCTOR DEVICES A method is presented for controlling the minority carrier lifetime in a semiconductor device by selectively implanting inert atoms such as helium, argon, neon, krypton, and xenon into specific regions of the device. The device structure is a bi-polar transistor having a region of inert atoms located in the collector adjacent to the base-collector junction. Another embodiment of the invention is a complementary insulated gate field effect transistor (IGFET) structure having N and P channel IGFETs with regions of implanted ions beneath the source and drain of one or both transistors, and/or annular regions projecting inwardly from the surface that surround or separate the different types of IGFETs.

公开(公告)号：FR2340621A1

公开(公告)日：1977-09-02

申请号：FR7623637

申请日：1976-07-27

Applicant: IBM

Inventor： JOY RICHARD C ,  MAGDO INGRID E ,  PHILLIPS ALFRED JR

IPC: H01L21/331 ,  H01L29/73 ,  H01L29/78 ,  H01L29/76

公开(公告)号：FR2320636A1

公开(公告)日：1977-03-04

申请号：FR7619836

申请日：1976-06-24

Applicant: IBM

Inventor： BURR PETER ,  JOY RICHARD C ,  ZIEGLER JAMES F

IPC: H01L27/08 ,  H01L21/265 ,  H01L21/322 ,  H01L21/331 ,  H01L21/76 ,  H01L21/8222 ,  H01L27/06 ,  H01L27/092 ,  H01L29/08 ,  H01L29/167 ,  H01L29/73 ,  H01L29/78 ,  H01L29/227

Abstract: The device structure is a bi-polar transistor having a region of inert atoms located in the collector adjacent to the base-collector junction. Another embodiment of the invention is a complementary insulated gate field effect transistor (IGFET) structure having N and P channel IGFETs with regions of implanted ions beneath the source and drain of one or both transistors, and/or annular regions projecting inwardly from the surface that surround or separate the different types of IGFETs.