SEMICONDUCTOR DEVICE COMPRISING A PLURALITY OF MEMORY STRUCTURES
    1.
    发明公开
    SEMICONDUCTOR DEVICE COMPRISING A PLURALITY OF MEMORY STRUCTURES 有权
    具有多存储器结构半导体元件

    公开(公告)号:EP1665344A4

    公开(公告)日:2007-07-18

    申请号:EP04784950

    申请日:2004-09-24

    Applicant: IBM

    CPC classification number: G06F12/0284

    Abstract: A structure and method of transferring data on a semiconductor device (2) having a plurality of systems (e.g. 6 and 3). Each system has at least one processing device (e.g. 7) and a local memory structure (e.g. 8). Each processing device is electrically coupled to each local memory structure within each system. Each local memory structure is electrically coupled to each of the other local memory structures. Each local memory structure is adapted to share address space with each of the processing devices. Each processing device is adapted to transmit data and instructions to each local memory structure.

    MESSAGE TERMINATION INFORMING METHOD AND SYSTEM THEREFOR, COMPUTER USABLE MEDIUM AND MEMORY

    公开(公告)号:JPH10301912A

    公开(公告)日:1998-11-13

    申请号:JP8862698

    申请日:1998-04-01

    Applicant: IBM

    Abstract: PROBLEM TO BE SOLVED: To inform a destination node of the termination of respective messages by setting a transmission origin start interruption field or a destination start interruption field inside the message, transmitting it and generating interruption in the destination node in response to the interruption fields at the time of the termination. SOLUTION: In the transmission origin node 181 of the message 40, the transmission origin start interruption (SII) field is set inside the message 40 and it is transmitted to the destination node 18N through a switch network 20. Then, in the destination node 18N, at the time of the termination of the message 40, the transmission start interruption (SII) 50 is performed in response to the SII field. Besides, for the different message among the plural messages, the destination start interruption (DII) field is set in the destination node 18N beforehand, and at the time of the termination of the message, the destination start interruption (DII) 60 is performed in the destination node in response to the DII field.

    SEMICONDUCTOR DEVICE COMPRISING A PLURALITY OF MEMORY STRUCTURES
    3.
    发明申请
    SEMICONDUCTOR DEVICE COMPRISING A PLURALITY OF MEMORY STRUCTURES 审中-公开
    包含大量存储器结构的半导体器件

    公开(公告)号:WO2005031804A3

    公开(公告)日:2006-07-20

    申请号:PCT/US2004031323

    申请日:2004-09-24

    CPC classification number: G06F12/0284

    Abstract: A structure and method of transferring data on a semiconductor device (2) having a plurality of systems (e.g. 6 and 3). Each system has at least one processing device (e.g. 7) and a local memory structure (e.g. 8). Each processing device is electrically coupled to each local memory structure within each system. Each local memory structure is electrically coupled to each of the other local memory structures. Each local memory structure is adapted to share address space with each of the processing devices. Each processing device is adapted to transmit data and instructions to each local memory structure.

    Abstract translation: 在具有多个系统(例如6和3)的半导体器件(2)上传送数据的结构和方法。 每个系统具有至少一个处理设备(例如7)和本地存储器结构(例如8)。 每个处理设备电耦合到每个系统内的每个本地存储器结构。 每个本地存储器结构电耦合到每个其他本地存储器结构。 每个本地存储器结构适于与每个处理设备共享地址空间。 每个处理设备适于将数据和指令传送到每个本地存储器结构。

    5.
    发明专利
    未知

    公开(公告)号:DE602004015125D1

    公开(公告)日:2008-08-28

    申请号:DE602004015125

    申请日:2004-09-24

    Applicant: IBM

    Abstract: A structure and associated method of transfer data on a semiconductor device, comprising: a plurality of systems within the semiconductor device. Each system comprises at least one processing device and a local memory structure. Each processing device is electrically coupled to each local memory structure within each system. Each local memory structure is electrically coupled to each of the other said local memory structures. Each local memory structure is adapted to share address space with each of the processing devices. Each processing device is adapted to transmit data and instructions to each local memory structure.

    SOURCE AND DESTINATION INITIATED INTERRUPT SYSTEM FOR MESSAGE ARRIVAL NOTIFICATION

    公开(公告)号:CA2231949A1

    公开(公告)日:1998-10-08

    申请号:CA2231949

    申请日:1998-03-11

    Applicant: IBM

    Abstract: A method, system, and associated program code and data structures are provided f or a message processing system in which messages are passed from source nodes to dest ination nodes. Notification of the arrival of the messages at the destination nodes can be effe cted by programmable source initiated interrupts or destination initiated interrupts. The source init iated interrupts are implemented as set fields embedded in the message packets sent from a source nod e to a destination node and trigger the requisite interrupt at the destination node upon message ar rival. The destination initiated interrupts are implemented as pre-set fields in anticipatory buffers w hich are allocated at the destination node for incoming messages from the source node. Standard incoming m essage queue polling, as well as interrupt enabling and disabling functions are also provided , which together allow the system to selectively invoke interrupt or alternative strategies to notify d estination nodes of arriving messages.

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