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公开(公告)号：JP2001195835A
公开(公告)日：2001-07-19
申请号：JP2000001140
申请日：2000-01-06
Applicant: IBM
Inventor： ONO HIROYUKI , ASANO HIDEO , KANAMARU ATSUSHI
Abstract: PROBLEM TO BE SOLVED: To prevent the deterioration in performance in reading the data in alternate sectors. SOLUTION: It is assumed that a write request of data (a) is made to a sector A, but since the sector A is a defective sector, the data is written into the alternate sector A' of an alternate sector region X. Next, when the write request for data (b) is made to a sector B, the alternate sector B' succeeding to the alternate sector A is subjected to reassignment. The defective sector C to which the write request for data (c) is made is similarly reassigned to the alternate sector C'. Accordingly, the continuous data (a), (b) and (c) are eventually written into the continuos sectors A', B' and C' within the same alternate sector X.
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公开(公告)号：DE10050171B4
公开(公告)日：2006-01-05
申请号：DE10050171
申请日：2000-10-11
Applicant: IBM
Inventor： KANAMARU ATSUSHI , ASANO HIDEO , KIBASHI AKIRA , SAITO TAKAHIRO , KOBAYASHI KEIJI
Abstract: A system and method are provided that reduce the amount of data held commonly in both high-ranking and low-ranking cache memories, thereby having each of those cache memories hold data more efficiently. More particularly, a computer system is provided with an HDC card 21 connected to an expansion bus 20 and an HDD unit 22 connected to the HDC card 21. The HDC card 21 is provided with a disk cache (high-ranking cache memory) and the HDD unit 22 is provided with a disk cache 54 (low-ranking cache memory). The HDC card 21 and the HDD unit 22 exchange select information for selecting a swap mode of each cache memory when the system is started up, thereby selecting different swap modes according to the exchanged select information respectively.
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公开(公告)号：JP2001125829A
公开(公告)日：2001-05-11
申请号：JP30660599
申请日：1999-10-28
Applicant: IBM , PROMISE TECHNOLOGY INC
Inventor： KANAMARU ATSUSHI , ASANO HIDEO , KIHASHI AKIRA , KUSHIDA KOICHI , SAITO TAKAHIRO , CHICHEN UU , KELVIN KAO
Abstract: PROBLEM TO BE SOLVED: To execute detailed analysis and prediction by an outside controller in reponse to a true request from an application, and to issue a look-ahead request to an auxiliary storage device such as an HDD. SOLUTION: An HDC card 21, which stores data and is connected to an HDD device 22 having a cache memory, is provided with an access request trace part 61 for directly tracing a true access request from an application program to be executed by a host from the application program, a speculative request deciding part 62 for deciding a speculative request estimated in the future based on the traced true access request, and an HDC 31 for issuing the decided speculative request to the HDD device 22.
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公开(公告)号：JP2003122631A
公开(公告)日：2003-04-25
申请号：JP2001316036
申请日：2001-10-12
Applicant: IBM
Inventor： KUSHIDA KOICHI , KANAMARU ATSUSHI , SAITO TAKAHIRO
Abstract: PROBLEM TO BE SOLVED: To efficiently execute a reading request issued from a host computer when a writing request is cached in a cache memory. SOLUTION: When a reading request is transferred, whether or not a cache memory is put into a memory state that the cache memory can cache the reading request is judged (S103). When it is impossible, the oldest writing request and the other prescribed writing request are executed after the order of execution is optimized so that the reading request can be cached by the cache memory (S107, S113). And, the cached reading request is executed preferentially to the writing request remaining in the cache memory by an RBPW (S111). Therefore, it is possible to efficiently execute the reading request.
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公开(公告)号：JP2001005616A
公开(公告)日：2001-01-12
申请号：JP16462599
申请日：1999-06-11
Applicant: IBM
Inventor： ONO HIROYUKI , ASANO HIDEO , KANAMARU ATSUSHI
Abstract: PROBLEM TO BE SOLVED: To eliminate a momentary decrease in performance as much as possible by performing a specific inspection regarding a function in a standby state wherein there is no access from a host. SOLUTION: It is judged whether the disk storage device is in standby mode (S1) and when not, commands from the host which are generated in a specific time are executed (S2) in current execution or after the execution temporarily ends. When it is judged that the device is in standby mode, a read test by a sequential read and a write servo test conducted by positioning a head at a write position are carried out so as to search for a bad sector and a write test by data writing to a specific sector is carried out to judge abnormality of the head. Consequently, when a bad sector is found through the read test or write servo test, it is formed in a preliminary area on a disk and reassigned to an alternative sector and when an abnormality of the head is found through the write test, that is reported to a user (S3).
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Patent Agency Ranking
公开(公告)号：JP2000163897A
公开(公告)日：2000-06-16
申请号：JP33568198
申请日：1998-11-26
Applicant: IBM
Inventor： KANAMARU ATSUSHI , ASANO HIDEO , UEDA TETSUO
IPC: G11B20/12 , G11B5/012 , G11B5/55 , G11B5/596 , G11B5/82 , G11B20/18 , G11B21/08 , G11B21/10 , G11B27/32
Abstract: PROBLEM TO BE SOLVED: To improve performance of a whole disk drive device while keeping the reliability. SOLUTION: Tracks used for the recording and tracks unused for the recording are alternately arranged in the specific areas of a magnetic disk 1. By a control part 3, the range of the specific areas is kept, and the threshold for detecting the completion of the seek against the tracks in the specific area is mitigated than the threshold for detecting the completion of the seek against the tracks out of the specific area.
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公开(公告)号：JPH10275110A
公开(公告)日：1998-10-13
申请号：JP7494997
申请日：1997-03-27
Applicant: IBM
Inventor： KANAMARU ATSUSHI , KAKIHARA TOSHIO , KIGAMI YUJI , SAITO TAKAHIRO
Abstract: PROBLEM TO BE SOLVED: To provide the disk drive device and its control method which can make an additional read of media at need while minimizing a command overhead, and then improve the total performance. SOLUTION: The disk drive device 10 performs data transfer until final one block is left and expects the intervention of the local MPU 16 even when HIC 15 is able to perform all data transfer without the intervention of a local MPU 16 while a read command is issued and requested data hit data held in a cache memory, the local MPU 16 makes an indication for transferring the final one block once preparations for the end of the command are made, and if there are more than one block of transfer data left when the local MPU 16 instructs the HIC 15 to transfer the final one block, the HIC 15 performs all the data transfer without interrupting the data transfer at the final one block, thus completing the command.
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公开(公告)号：JPH10255403A
公开(公告)日：1998-09-25
申请号：JP5775197
申请日：1997-03-12
Applicant: IBM
Inventor： KAKIHARA TOSHIO , KANAMARU ATSUSHI , SATO TAKUMI , SATO MASAHIKO
Abstract: PROBLEM TO BE SOLVED: To reduce the error processing time during a reset, by executing a first error recovering processing while controlling a write controlling means if a writing error is detected and executing a second error recovering processing, which is small in the number of execution commands than an error recovering processing(ERP), while controlling the means if a reset instruction is detected. SOLUTION: If a reset is requested, a control section 3 does not execute the ERP, the selector being selected is assumed to be defective, the temporary registration processing of the defective sector is conducted, the assignment of a spare sector is made and the updating of a reassigned table is executed. In the normal ERP having no reset request, many processings are repeated from such a judgement that is not a reset, up to the judgement of an error recovering impossible. Thus, the number of steps, which are actually to be executed, becomes extremely large. Therefore, the time required to execute the processings greatly differs for between the case of a reset is requested and the case in which no request is made for a reset.
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公开(公告)号：MY118820A
公开(公告)日：2005-01-31
申请号：MYPI9800731
申请日：1998-02-20
Applicant: IBM
Inventor： KANAMARU ATSUSHI , KAKIHARA TOSHIO , KIGAMI YUHJI , SAITOH TAKAHIRO
Abstract: A DISK DRIVE AND A METHOD FOR CONTROLLING THE DISK DRIVE IN WHICH AN ADDITIONAL READ FROM A MEDIUM CAN BE PERFORMED AS NEEDED WHILE MINIMIZING THE COMMAND OVERHEAD TO THE MINIMUM. IN A DISK DRIVE DEVICE (10), EVEN IF A READ COMMAND IS ISSUED, AND ALL THE REQUIRED DATA IS STORED IN THE CACHE MEMORY SUCH THAT THE DATA TRANSFER CAN BE PERFORMED WITHOUT THE INTERVENTION OF A LOCAL MPU (16), A HIC (15) PERFORMS THE DATA TRANSFER SO AS TO LEAVE THE LAST ONE BLOCK AND WAITS FOR THE INTERVENTION OF THE LOCAL MPU (16). THE LOCAL MPU (16) PROVIDES INSTRUCTIONS TO TRANSFER THE LAST ONE BLOCK WHEN THE PREPARATION FOR THE COMMAND TERMINATION IS COMPLETED, AND IF A PLURALITY OF BLOCKS OF DATA TO BE TRANSFERRED ARE REMAINING WHEN THE LOCAL MPU (16) INSTRUCTS THE HIC (15) TO TRANSFER THE LAST ONE BLOCK, THE HIC (15) EXECUTES ALL THE DATA TRANSFER WITHOUT STOPPING THE DATA TRANSFER BEFORE THE LAST ONE BLOCK, COMPLETING THE COMMAND.FIGURE 1
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公开(公告)号：DE10050171A1
公开(公告)日：2001-04-19
申请号：DE10050171
申请日：2000-10-11
Applicant: IBM
Inventor： KANAMARU ATSUSHI , ASANO HIDEO , KIBASHI AKIRA , SAITO TAKAHIRO , KOBAYASHI KEIJI
Abstract: Involves operating high order cache-memory and the low order cache-memory in different data 'exchange' modes. When a system is accelerated or run up to speed, an exchange of selected data for selecting a data 'exchange' mode for each cache-memory between the cache-memory of the high order and the cache-memory of the low order, takes place. Avoidance of errors in data storage in cache-memories used in computer systems based on hard-disc drives (HDDs) and with high and low order cache-memories being used and operated in different data 'exchange' modes, such as the least recently used (LRU) and least frequently used (LFU) modes, when a cache-memory has no free data storage locations available, involves operating the high order cache-memory and the low order cache-memory in different data 'exchange' modes, and when a system is accelerated or run up to speed, an exchange of selected data for selecting a data 'exchange' mode for each cache-memory between the cache-memory of the high order and the cache-memory of the low order, takes place..
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