FIELD EFFECT TRANSISTOR AND FABRICATION THEREOF

    公开(公告)号:JPH1070274A

    公开(公告)日:1998-03-10

    申请号:JP19095797

    申请日:1997-07-16

    Applicant: IBM

    Abstract: PROBLEM TO BE SOLVED: To decrease the gate resistance significantly by forming a Schottky metal ohmic source/drain contact or an epitaxial ohmic contact and a self- aligned T type metal or a metal/polisilicon gate. SOLUTION: A sacrifice layer 14, a metal layer 16 eventually forming a Schottky barrier or a junction to a channel and an insulation layer 18 are formed on a substrate 12. The insulation layer 18 is applied with a resist and a lithography pattern is formed thus defining a gate window 19. The metal layer 16 and the sacrifice layer 14 are then alloyed to form a source-contact 22 without disturbing the sacrifice layer 14 in the gate window 19. The source- contact and a drain contact 22 form a Schottky barrier or junctions 23, 24 thus forming a channel 25 in the substrate 12. Thereafter, the sacrifice layer 14 is removed from the gate window 19 and a gate oxide 26 is deposited on the substrate 12 in the gate window 19 and on the side wall 27, 28 and the upper surface of the insulation layer 18.

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