Abstract:
A light emitting device comprises a gate electrode (101), a channel (103) comprising a molecule for electrically stimulated optical emission, wherein the molecule is disposed within an effective range of the gate electrode (101), a source (104) coupled to a first end of the channel injecting electrons into the channel, and a drain (105) coupled to a second end of the channel injecting holes into the channel.
Abstract:
PROBLEM TO BE SOLVED: To provide a silicide treating method for thin-film SOI device. SOLUTION: The self-aligned silicide-process contains a step for attaching a metal or an alloy the gate, source and drain structures formed on an SOI film a step for forming a first alloy by reacting the metal or the alloy with the SOI film at a first temperature, a step, for selectively etching the nonreactive layer of the metal (or the alloy), a step for attaching an Si film on the first alloy, a step for forming a second alloy by reacting the Si film at the second temperature and a step for selectively etching the nonreactive layer of the Si film.
Abstract:
A light emitting device comprises a gate electrode (101), a channel (103) comprising a molecule for electrically stimulated optical emission, wherein the molecule is disposed within an effective range of the gate electrode (101), a source (104) coupled to a first end of the channel injecting electrons into the channel, and a drain (105) coupled to a second end of the channel injecting holes into the channel.
Abstract:
PROBLEM TO BE SOLVED: To provide a vertical FET including a nanowire channel, with the access resistance to the lower contact reduced and the gate length controlled. SOLUTION: A vertical FET structure, having a nanowire which constitutes a FET channel, is disclosed. A nanowire is formed on a conductive silicide layer. The nanowire is controlled by a gate surrounding it. Upper and lower insulating plugs function as gate spacers and make the gate-source capacitance and the gate-drain capacitance reduced. COPYRIGHT: (C)2007,JPO&INPIT
Abstract:
PROBLEM TO BE SOLVED: To provide a method of manufacturing a FinFET, having a strained-silicon channel (and the structure obtained). SOLUTION: A semiconductor device (and the method of manufacturing the same) includes the strained-silicon channel formed adjacent to the source and the drain, a first gate formed on the first side section of the channel, a second gate formed on the second side section of the channel, a first gate dielectric formed between the first gate and the strained-silicon channel, and a second gate dielectric formed between the second gate and the strained-silicon channel. The strained-silicon channel is nonplanar. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract:
PROBLEM TO BE SOLVED: To provide a high-speed photodiode which essentially has very few slow carrier and substantially produces no etalon effect. SOLUTION: This high-speed photodiode comprises a photodetector 110, a substrate 100A formed below the photodetector, and a barrier layer 105 formed on the substrate. The embedded barrier layer includes a single/double pn junction or a bubble layer to block or remove slow photon generation carriers in a region with a low drift field. COPYRIGHT: (C)2004,JPO&NCIPI
Abstract:
PROBLEM TO BE SOLVED: To provide a self-aligned silicide process applicable to contacting silicon, sidewall, source, and drain. SOLUTION: A method (and a structure formed by using this method) to form a metal silicide contact on a non-planar silicon-containing area which limits the silicon consumption at a silicon-containing area includes: forming a blanket metal layer over the silicon-containing area, forming a silicon layer over the metal layer, performing an selective and anisotropical etching of the silicon layer against the metal, forming a metal silicon alloy by reacting the metal and silicon at a first temperature, etching away any unreacted metal layer, forming a metal-Si2 alloy by annealing at a second temperature, and selectively etching away any unreacted silicon layer.
Abstract:
PROBLEM TO BE SOLVED: To provide a method for manufacturing micro-structures, such as micro-electromechanical structures (MEMS) or silicon optical benches. SOLUTION: The method includes using a single mask to pattern a plurality of cavity areas to be etched on a substrate in different etching steps, and then selectively choosing the cavity areas for etching. In a preferred embodiment, the method includes patterning a substrate to identify a plurality of cavity areas to be etched on the substrate and filling at least one of the cavity areas with a distinctive filler material. The filler material is chemically distinctive in the sense that it can be etched selectively with respect to the other filling materials 203, 205, 206, 207. The methods of the invention produce micro- structures with more accurate cavity areas by minimizing overlay error and avoiding the need for lithography over extreme topography. COPYRIGHT: (C)2003,JPO
Abstract:
PROBLEM TO BE SOLVED: To provide a method for forming a pattern formation buried oxide film. SOLUTION: The method for forming the pattern formation buried oxide film comprises a step of carrying out implantation into a substrate, a step of forming a mask at least on part of the substrate in order to control implantation diffusion, and a step of annealing the substrate and forming a buried oxide. The mask can be selectively pattern-formed. A thinner buried oxide can be formed in a region coated by the mask than in a region exposed to an annealing atmosphere directly.
Abstract:
A light emitting device comprises a gate electrode, a channel comprising a molecule for electrically stimulated optical emission, wherein the molecule is disposed within an effective range of the gate electrode, a source coupled to a first end of the channel injecting electrons into the channel, and a drain coupled to a second end of the channel injecting holes into the channel.