Storage circuit block and data write-in method
    1.
    发明专利
    Storage circuit block and data write-in method 有权
    存储电路块和数据写入方法

    公开(公告)号:JP2003016774A

    公开(公告)日:2003-01-17

    申请号:JP2001194227

    申请日:2001-06-27

    Abstract: PROBLEM TO BE SOLVED: To solve such a problem that because a current is required to make to flow for each bit line when data are written simultaneously in a plurality of data bits belonging to the same column address, a current required for write-in is enlarged.
    SOLUTION: This device comprises a plurality of pairs of bit line comprising a first bit line and a second bit line, a plurality of storage cells storing information in accordance with the direction of a current flowing in the pair of bit line, at least one current driving source connected to at least one of pairs of bit line and making to flow a current in the first bit line and the second bit line of which the directions of current are reverse each other, at least one switch circuit connecting pairs of bit line and pairs of bit line, and a control circuit controlling a connection state of the switch circuit in accordance with information stored in the storage cell.
    COPYRIGHT: (C)2003,JPO

    Abstract translation: 要解决的问题:为了解决由于在属于同一列地址的多个数据位中同时写入数据时需要为每个位线流动电流的问题,写入所需的电流为 放大 解决方案:该装置包括多对位线,包括第一位线和第二位线,多个存储单元根据在一对位线中流动的电流的方向存储信息,至少一个电流 驱动源连接到位线对中的至少一个并使得流过第一位线中的电流,并且使电流方向彼此相反的第二位线,至少一个连接成对的位线和 一对位线,以及根据存储在存储单元中的信息来控制开关电路的连接状态的控制电路。

    NON-VOLATILE MEMORY DEVICE
    3.
    发明专利

    公开(公告)号:JP2002230965A

    公开(公告)日:2002-08-16

    申请号:JP2001015475

    申请日:2001-01-24

    Applicant: IBM

    Abstract: PROBLEM TO BE SOLVED: To improve the reliability of recording of a MRAM. SOLUTION: This device has read-out word lines WLR and write-in word lines WLW extending in the direction of (y), and write-in read-out bit lines BLW/R and write-in bit lines BLW extending in the direction of (x), and a memory cell MC is arranged at an intersection of a word line and a bit line. The memory cell MC comprises a sub-cell SC1 and a sub-cell SC2, the sub-cell SC1 comprises magnetic resistance elements MTJ1, MTJ2, and a selection transistor Tr1, and the sub-cell SC2 comprises magnetic resistance elements MTJ3, MTJ4, and a selection transistor Tr2, and the sub-cell SC2, The magnetic resistance elements MTJ1 and MTJ2 are connected in parallel, also, the magnetic resistance elements MTJ3 and MTJ2 are connected in parallel. The sub- cells SC1 and SC2 are connected in series between the write-in read-out bit lines BLW/R and ground.

    DEHUMIDIFIER, DEHUMIDIFYING UNIT, DISC DRIVE AND DEHUMIDIFICATION CONTROL SYSTEM

    公开(公告)号:JP2001194023A

    公开(公告)日:2001-07-17

    申请号:JP2000000193

    申请日:2000-01-05

    Applicant: IBM

    Abstract: PROBLEM TO BE SOLVED: To provide a dehumidifier which can be fixed to a small space of the cover of a disc drive and can sustain the inner humidity of the disc drive at a low level permanently, and to perform dehumidification stably without forming any dew on the inside or the outside of the disc drive by controlling the dehumidifier based on the inner humidity or the temperature conditions on the inside and the outside of the disc drive. SOLUTION: The dehumidifier comprises glass fibers 55 disposed to penetrate the cover 3 of a hard disc drive HDD and extending over the inside and outside thereof, and a heating member 53 disposed on the outside of the HDD wherein the glass fibers 55 on the outside are bonded to the heating member and heated. Furthermore, a cooling member is provided on the inside of the HDD and the glass fibers on the inside are bonded to the cooling member. Means for circulating air touching a heating part and cooling part is also provided.

    MAGNETIC HEAD AND MANUFACTURE THEREOF

    公开(公告)号:JPH04337509A

    公开(公告)日:1992-11-25

    申请号:JP12312591

    申请日:1991-04-26

    Applicant: IBM

    Abstract: PURPOSE: To embody high-density recording by a ferrite head by joining the bonding bumps of two chips, thereby forming a winding coil. CONSTITUTION: The chip 1 is formed with multilayered wirings 10 and the bonding bumps 13 on an Si substrate 12. The chip 2 is formed with the multilayered wirings 10 of copper, conducting paths 14 penetrating the substrate, the bonding bumps 13 and grooves 6 for crossing the ferrite cores. The bonding bumps 13 are composed of a low melting solder and are melted by a heat treatment at about 150 deg.C. The chips 1 and 2 are joined by melting the bonding bumps 13, by which the winding coil is formed.

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