公开(公告)号：AT552533T

公开(公告)日：2012-04-15

申请号：AT06793213

申请日：2006-09-05

Applicant: IBM

Inventor： HOLMES STEVEN ,  FURUKAWA TOSHIHARU ,  KOBURGER CHARLES ,  MOUMEN NAIM

IPC: G03F7/20 ,  G03F7/11

Abstract: An immersion lithography system is provided which includes an optical source operable to produce light having a nominal wavelength and an optical imaging system. The optical imaging system has an optical element in an optical path from the optical source to an article to be patterned thereby. The optical element has a face which is adapted to contact a liquid occupying a space between the face and the article. The optical element includes a material which is degradable by the liquid and a protective coating which covers the degradable material at the face for protecting the face from the liquid, the protective coating being transparent to the light, stable when exposed to the light and stable when exposed to the liquid.

公开(公告)号：AT504946T

公开(公告)日：2011-04-15

申请号：AT05707994

申请日：2005-02-10

Applicant: IBM

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK ,  HOLMES STEVEN ,  HORAK DAVID ,  KOBURGER CHARLES ,  MITCHELL PETER ,  NESBIT LARRY

IPC: H01L51/05 ,  G11C13/02 ,  H01L21/335 ,  H01L21/336 ,  H01L27/28 ,  H01L29/06 ,  H01L29/12 ,  H01L29/772 ,  H01L51/30 ,  H01L51/40

Abstract: Carbon nanotube field effect transistors, arrays of carbon nanotube field effect transistors, device structures, and arrays of device structures. A stacked device structure includes a gate electrode layer and catalyst pads each coupled electrically with a source/drain contact. The gate electrode layer is divided into multiple gate electrodes and at least one semiconducting carbon nanotube is synthesized by a chemical vapor deposition process on each of the catalyst pads. The gate electrode has a sidewall covered by a gate dielectric and at least one semiconducting carbon nanotube adjacent to the sidewall of the gate electrode. Source/drain contacts are electrically coupled with opposite ends of the semiconducting carbon nanotube to complete the device structure. Multiple device structures may be configured either as a memory circuit or as a logic circuit.