Abstract:
An immersion lithography system is provided which includes an optical source operable to produce light having a nominal wavelength and an optical imaging system. The optical imaging system has an optical element in an optical path from the optical source to an article to be patterned thereby. The optical element has a face which is adapted to contact a liquid occupying a space between the face and the article. The optical element includes a material which is degradable by the liquid and a protective coating which covers the degradable material at the face for protecting the face from the liquid, the protective coating being transparent to the light, stable when exposed to the light and stable when exposed to the liquid.
Abstract:
An immersion lithography system is provided which includes an optical source operable to produce light having a nominal wavelength and an optical imaging system. The optical imaging system has an optical element in an optical path from the optical source to an article to be patterned thereby. The optical element has a face which is adapted to contact a liquid occupying a space between the face and the article. The optical element includes a material which is degradable by the liquid and a protective coating which covers the degradable material at the face for protecting the face from the liquid, the protective coating being transparent to the light, stable when exposed to the light and stable when exposed to the liquid.
Abstract:
PROBLEM TO BE SOLVED: To provide a structure and manufacturing method of a notch gate field effect transistor which can cope with a problem of device (element) reliability. SOLUTION: A gate dielectric 14 (for example, gate oxide film) is preferably formed on a surface of an active field 10 on a semiconductor substrate defined by a separation trench area 12. Next, a polysilicon layer 16 is accumulated on the gate dielectric. After the above process, a silicon germanium (SiGe) layer 18 is accumulated. Next, a side wall of the polysilicon layer is selectively etched in the transverse direction against the SiGe layer, and a notch gate conductor structure having the SiGe layer wider than the polysilicon layer thereunder is formed. A side wall spacer 26 is formed preferably on the side wall of the SiGe layer and the polysilicon layer. In order to reduce the resistance of a gate conductor 24, preferably, a silicide layer 28 is formed as self-alignment silicide from the polysilicon layer accumulated on the SiGe layer. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract:
Electrical contact to the front side of a photovoltaic cell is provided by an array of conductive through-substrate vias, and optionally, an array of conductive blocks located on the front side of the photovoltaic cell. A dielectric liner provides electrical isolation of each conductive through-substrate via from the semiconductor material of the photovoltaic cell. A dielectric layer on the backside of the photovoltaic cell is patterned to cover a contiguous region including all of the conductive through-substrate vias, while exposing a portion of the backside of the photovoltaic cell. A conductive material layer is deposited on the back surface of the photovoltaic cell, and is patterned to form a first conductive wiring structure that electrically connects the conductive through-substrate vias and a second conductive wiring structure that provides electrical connection to the backside of the photovoltaic cell.
Abstract:
A gate structure (200) for complementary metal oxide semiconductor (CMOS) devices includes a first gate stack (116) having a first gate dielectric layer (102) formed over a substrate (100), and a first metal layer (106) formed over the first gate dielectric layer. A second gate stack (118) includes a second gate dielectric layer (102) formed over the substrate and a second metal layer (110) formed over the second gate dielectric layer. The first metal layer is formed in manner so as to impart a tensile stress on the substrate, and the second metal layer is formed in a manner so as to impart a compressive stress on the substrate.
Abstract:
Durch eine Anordnung von leitenden Durchkontaktierungen durch ein Substrat und optional durch eine Anordnung von leitenden Blöcken, die sich auf der Vorderseite einer Photovoltaikzelle befindet, wird ein elektrischer Kontakt mit der Vorderseite der Photovoltaikzelle bereitgestellt. Eine dielektrische Auskleidung stellt eine elektrische Trennung jeder leitenden Durchkontaktierung durch das Substrat gegenüber dem Halbleitermaterial der Photovoltaikzelle bereit. Eine dielektrische Schicht auf der Rückseite der Photovoltaikzelle ist so strukturiert, dass sie einen zusammenhängenden Bereich abdeckt, der alle leitenden Durchkontaktierungen durch das Substrat beinhaltet, während sie einen Abschnitt der Rückseite der Photovoltaikzelle freilegt. Eine Schicht eines leitenden Materials wird auf der Rückfläche der Photovoltaikzelle abgeschieden und so strukturiert, dass sie eine erste leitende Verdrahtungsstruktur, die die leitenden Durchkontaktierungen durch das Substrat elektrisch verbindet, und eine zweite leitende Verdrahtungsstruktur ausbildet, die eine elektrische Verbindung mit der Rückfläche der Photovoltaikzelle bereitstellt.
Abstract:
An immersion lithography system is provided which includes an optical source operable to produce light having a nominal wavelength and an optical imaging system. The optical imaging system has an optical element in an optical path from the optical source to an article to be patterned thereby. The optical element has a face which is adapted to contact a liquid occupying a space between the face and the article. The optical element includes a material which is degradable by the liquid and a protective coating which covers the degradable material at the face for protecting the face from the liquid, the protective coating being transparent to the light, stable when exposed to the light and stable when exposed to the liquid.