公开(公告)号：JP2010153788A

公开(公告)日：2010-07-08

申请号：JP2009229804

申请日：2009-10-01

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： EDWARD J NOWACK ,  SLINKMAN JAMES ALBERT ,  BOTULA ALAN BERNARD

IPC: H01L29/786 ,  H01L21/3205 ,  H01L21/76 ,  H01L21/762 ,  H01L21/768 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8234 ,  H01L23/52 ,  H01L27/04 ,  H01L27/08 ,  H01L27/088 ,  H01L29/417

CPC classification number: H01L21/84 ,  H01L21/76224 ,  H01L21/76251 ,  H01L27/1203

Abstract: PROBLEM TO BE SOLVED: To provide an integrated circuit which is reduced in capacitive coupling of a semiconductor-on-insulator (SOI) substrate.
SOLUTION: First doped semiconductor regions 18 having the same conductivity type dopant as a bottom semiconductor layer and second doped semiconductor regions 28 having an opposite conductivity type dopant are formed directly underneath a buried insulator layer 20 of the (SOI) substrate. The first doped semiconductor regions 18 and the second doped semiconductor regions 28 are electrically grounded or forward-biased relative to the bottom semiconductor layer at a voltage that is insufficient to cause excessive current due to forward-biased injection of minority carriers into the bottom semiconductor layer, i.e., at a potential difference not exceeding 0.6V to 0.8V. The electrical charges formed in an induced charge layer by the electrical signal in semiconductor devices on the top semiconductor layer are drawn through electrical contacts connected to the first and the second doped semiconductor regions, thereby reducing harmonic signals in the semiconductor devices.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供减小绝缘体上半导体（SOI）衬底的电容耦合的集成电路。 解决方案：具有与半导体层相同的导电类型掺杂剂的第一掺杂半导体区域18和具有相反导电型掺杂剂的第二掺杂半导体区域28直接形成在（SOI）衬底的掩埋绝缘体层20的下方。 第一掺杂半导体区域18和第二掺杂半导体区域28相对于底部半导体层以不足以引起由于少数载流子正向偏置注入底部半导体层而导致过大电流的电压而被电接地或正向偏置 即电位差不超过0.6V至0.8V。 通过在顶部半导体层上的半导体器件中的电信号在感应电荷层中形成的电荷通过连接到第一和第二掺杂半导体区域的电触点而被拉出，从而减少半导体器件中的谐波信号。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2010153786A

公开(公告)日：2010-07-08

申请号：JP2009224423

申请日：2009-09-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： SHI YUN ,  BOTULA ALAN BERNARD ,  JOSEPH ALVIN JOSE ,  SLINKMAN JAMES ALBERT ,  EDWARD J NOWAKU

IPC: H01L29/786 ,  H01L21/3205 ,  H01L21/76 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L23/52 ,  H01L27/04 ,  H01L27/08

CPC classification number: H01L27/1203 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/76251 ,  H01L21/84

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor structure capable of performing signal isolation which is enhanced with respect to a semiconductor device from a bottom semiconductor layer in an SOI (Semiconductor On Insulator) substrate, a method for manufacturing the semiconductor structure, and a method for operating the semiconductor structure. SOLUTION: In a method for forming a semiconductor structure, a doped contact region 18 having an opposite conductivity type as a bottom semiconductor layer 10 is provided under a buried insulator layer 20 in the bottom semiconductor layer 10, and at least one conductive via structure 47 and 77 extends from an interconnect-level metal line 94 through a middle-of-line (MOL) dielectric layer 80, a shallow trench isolation structure 33 in a top semiconductor layer 30, and a buried insulator layer 20 to the doped contact region 18. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：为了提供一种能够执行信号隔离的半导体结构，其在SOI（半导体绝缘体）衬底中的底部半导体层相对于半导体器件增强，半导体结构的制造方法， 以及用于操作半导体结构的方法。 解决方案：在用于形成半导体结构的方法中，在底部半导体层10中的掩埋绝缘体层20的下方设置具有与底部半导体层10相反的导电类型的掺杂接触区域18，并且至少一个导电 通孔结构47和77从互连级金属线94延伸穿过中间线（MOL）电介质层80，顶部半导体层30中的浅沟槽隔离结构33和掺杂的 联系区域18.版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2001298188A

公开(公告)日：2001-10-26

申请号：JP2001083621

申请日：2001-03-22

Applicant: IBM

Inventor： JEFFREY SCOTT BROWN ,  FURKAY STEPHEN SCOTT ,  GAUTHIER ROBERT J JR ,  MARTIN DALE WARNER ,  SLINKMAN JAMES ALBERT

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/335 ,  H01L21/336 ,  H01L29/10

Abstract: PROBLEM TO BE SOLVED: To provide an FET where an inverse short channel effect is reduced as well as a method for forming it. SOLUTION: Germanium is so implanted over the entire semiconductor substrate at an appropriate intensity and quantity that a peak ion concentration is generated under the source and drain of the FET. The germanium is implanted before the gate, source, and drain are formed, so an inversion short channel effect which is shown with normal FETs is reduced. The short channel effect occurring with the normal FETs is never affected by implantation of germanium.

公开(公告)号：JP2010157699A

公开(公告)日：2010-07-15

申请号：JP2009268806

申请日：2009-11-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BOTULA ALAN BERNARD ,  GAUTSCH MICHAEL LAWRENCE ,  LEVY MAX GERALD ,  JOSEPH ALVIN JOSE ,  SLINKMAN JAMES ALBERT

IPC: H01L21/76 ,  H01L21/265 ,  H01L21/762 ,  H01L27/12

CPC classification number: H01L21/76283

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a trench in an electric structure.
SOLUTION: This method of forming the trench includes preparing a semiconductor structure including a semiconductor substrate, a burying oxide (BOX) layer formed on the semiconductor substrate, and a silicon-on-insulator layer (SOI) formed on the BOX layer in a state in contact with it. The SOI layer includes a shallow trench isolation (STI) structure formed between electric devices. A first photoresist layer is formed on the STI structure and the electric devices. A trench is formed by removing the part of the first photoresist layer, the part of the STI structure and the part of the BOX layer. An ion implantation part is formed in a part of the semiconductor substrate. The residual part of the first photoresist layer is removed. A dielectric layer is formed on the electric devices and in the trench. A second photoresist layer is formed on the dielectric layer. The part of the second photoresist layer is removed.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种在电气结构中形成沟槽的方法。 解决方案：这种形成沟槽的方法包括制备半导体结构，其包括形成在半导体衬底上的半导体衬底，埋入氧化物（BOX）层和形成在BOX层上的绝缘体上硅层 处于与之接触的状态。 SOI层包括在电子器件之间形成的浅沟槽隔离（STI）结构。 在STI结构和电气装置上形成第一光致抗蚀剂层。 通过去除第一光致抗蚀剂层的一部分，STI结构的一部分和BOX层的一部分来形成沟槽。 在半导体衬底的一部分中形成离子注入部。 去除第一光致抗蚀剂层的残留部分。 在电气设备和沟槽中形成电介质层。 在介电层上形成第二光致抗蚀剂层。 去除第二光致抗蚀剂层的一部分。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：CA2559219A1

公开(公告)日：2005-10-13

申请号：CA2559219

申请日：2005-03-22

Applicant: IBM

Inventor： SLINKMAN JAMES ALBERT ,  KOBURGER CHARLES WILLIAM III ,  FURUKAWA TOSHIHARU

IPC: H01L21/84 ,  H01L21/336 ,  H01L21/762 ,  H01L27/12 ,  H01L29/786

Abstract: A silicon-on-insulator (SOI) device and structure having locally strained regions in the silicon active layer formed by increasing the thickness of underlying regions of a buried insulating layer separating the silicon active layer from the substrate. The stress transferred from the underlying thickened regions of the insulating layer to the overlying strained regions increases carrier mobility in these confined regions of the active layer. Devices formed in and on the silicon active layer may benefit from the increased carrier mobility in the spaced-apart strained regions.

公开(公告)号：CA2559219C

公开(公告)日：2010-11-02

申请号：CA2559219

申请日：2005-03-22

Applicant: IBM

Inventor： FURUKAWA TOSHIHARU ,  KOBURGER CHARLES WILLIAM III ,  SLINKMAN JAMES ALBERT

IPC: H01L21/84 ,  H01L21/336 ,  H01L21/762 ,  H01L27/12 ,  H01L29/786

Abstract: A silicon-on-insulator (SOI) device and structure having locally strained regions in the silicon active layer formed by increasing the thickness of underlying regions of a buried insulating layer separating the silicon active layer from the substrate. The stress transferred from the underlying thickened regions of the insulating layer to the overlying strained regions increases carrier mobility in these confined regions of the active layer. Devices formed in and on the silicon active layer may benefit from the increased carrier mobility in the spaced-apart strained regions.

公开(公告)号：MXPA06007643A

公开(公告)日：2006-09-04

申请号：MXPA06007643

申请日：2005-03-22

Applicant: IBM

Inventor： SLINKMAN JAMES ALBERT

IPC: H01L21/762 ,  H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786

Abstract: Se describe un dispositivo y estructura de silicio sobre aislante (SOI) que tiene regiones deformadas localmente en la capa activa de silicio formadas al incrementar el espesor de las regiones subyacentes de una capa aislante enterrada que separa la capa activa de silicio del sustrato. El esfuerzo transferido desde las regiones engrosadas subyacentes de la capa aislante a las regiones deformadas superpuestas incrementa la movilidad portadora en estas regiones confinadas de la capa activa. Los dispositivos formados en y sobre la capa activa de silicio se pueden beneficiar de la movilidad portadora incrementada en las regiones deformadoras espaciadas igualmente.

公开(公告)号：IN261DEN2015A

公开(公告)日：2015-07-10

申请号：IN261DEN2015

申请日：2015-01-12

Applicant: IBM

Inventor： FURUKAWA TOSHIHARU ,  KOBURGER III CHARLES WILLIAM ,  SLINKMAN JAMES ALBERT

IPC: H01L27/12 ,  H01L21/336 ,  H01L21/762 ,  H01L21/84 ,  H01L29/786

Abstract: A silicon-on-insulator (SOI) device and structure having locally strained regions in the silicon active layer formed by increasing the thickness of underlying regions of a buried insulating layer separating the silicon active layer from the substrate. The stress transferred from the underlying thickened regions of the insulating layer to the overlying strained regions increases carrier mobility in these confined regions of the active layer. Devices formed in and on the silicon active layer may benefit from the increased carrier mobility in the spaced-apart strained regions.

公开(公告)号：DE602005007592D1

公开(公告)日：2008-07-31

申请号：DE602005007592

申请日：2005-03-22

Applicant: IBM

Inventor： FURUKAWA TOSHIHARU ,  KOBURGER III CHARLES ,  SLINKMAN JAMES ALBERT

IPC: H01L21/84 ,  H01L21/336 ,  H01L21/762 ,  H01L27/12 ,  H01L29/786

Abstract: A silicon-on-insulator (SOI) device and structure having locally strained regions in the silicon active layer formed by increasing the thickness of underlying regions of a buried insulating layer separating the silicon active layer from the substrate. The stress transferred from the underlying thickened regions of the insulating layer to the overlying strained regions increases carrier mobility in these confined regions of the active layer. Devices formed in and on the silicon active layer may benefit from the increased carrier mobility in the spaced-apart strained regions.