SUBSTRATE FOR INTEGRATED CIRCUIT PACKAGES

    公开(公告)号:DE3379820D1

    公开(公告)日:1989-06-08

    申请号:DE3379820

    申请日:1983-06-01

    Applicant: IBM

    Abstract: A method of preparing a conductor for solder bonding and a substrate to which this method may be applied. The method involves the use of three layers comprising a conductor layer 32, a barrier layer 33 and a solder wettable layer 35'. Solder bonds may be made to this solder wettable layer. During thermal cycling there may, in the absence of the barrier layer, be a tendency for material from the conductor layer to diffuse into the solder wettable layer and thence into the solder where it can form intermetallic alloys with Sn in the solder, causing the solder to become brittle and liable to failure. The inclusion of a barrier layer of suitable material, eg Cr or Co, reduces this diffusion and hence increases the reliability of the solder bonds. Optionally, the method includes provision for solderless bonding by thermocompression or ultrasonic bonding. This may be performed on the barrier layer at 37 or it may be performed elsewhere.

    7.
    发明专利
    未知

    公开(公告)号:DE2729074A1

    公开(公告)日:1978-03-09

    申请号:DE2729074

    申请日:1977-06-28

    Applicant: IBM

    Abstract: The operational heat of a semiconductor chip (1) is transferred to a cooling can (5) by means of a metal cushion (7). The metal cushion is permanently connected to the can or the chip on one side whilst its opposite side is in loose contact. This creates a connection of high thermal conductivity without exposing the chip to inadmissible mechanical stresses.

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