公开(公告)号：US3230387A

公开(公告)日：1966-01-18

申请号：US10337461

申请日：1961-04-17

Applicant: IBM

Inventor： GRUODIS ALGIRDAS J ,  LANGE LAWRENCE K ,  MCANNEY WILLIAM H

IPC: H03K19/10

CPC classification number: H03K19/10

公开(公告)号：US3348033A

公开(公告)日：1967-10-17

申请号：US47858565

申请日：1965-08-10

Applicant: IBM

Inventor： GRUODIS ALGIRDAS J ,  LANGE LAWRENCE K ,  MCANNEY WILLIAM H

IPC: G06F7/50 ,  G06F7/501 ,  H03K19/10

CPC classification number: G06F7/5013 ,  G06F2207/4828 ,  H03K19/10

公开(公告)号：US3155845A

公开(公告)日：1964-11-03

申请号：US16332361

申请日：1961-12-29

Applicant: IBM

Inventor： GRUODIS ALGIRDAS J ,  LANGE LAWRENCE K ,  MCANNEY WILLIAM H

IPC: H03K3/2893 ,  H03K19/082 ,  H03M5/18

CPC classification number: H03K3/2893 ,  H03K19/0823 ,  H03M5/18

公开(公告)号：JPS6115238A

公开(公告)日：1986-01-23

申请号：JP4500985

申请日：1985-03-08

Applicant: Ibm

Inventor： AICHELMANN JR FREDERICK J ,  LANGE LAWRENCE K

IPC: G06F12/16 ,  G06F11/10 ,  H03M13/00

CPC classification number: G06F11/1028

Abstract: An error correction code, especially suited for memory chips with multi-bit outputs, in which parity bits are calculated for each byte of the word and check bits are calculated for the word as a whole. In a 4-byte, 32-bit word, eight bits of error correction can correct up to four errors if the errors are restricted to corresponding bits in the 4 bytes.

公开(公告)号：DE3380150D1

公开(公告)日：1989-08-10

申请号：DE3380150

申请日：1983-09-20

Applicant: IBM

Inventor： AICHELMANN FREDERICK J ,  LANGE LAWRENCE K

IPC: G06F12/16 ,  G11C29/00 ,  G06F11/00

公开(公告)号：DE3380910D1

公开(公告)日：1990-01-04

申请号：DE3380910

申请日：1983-05-27

Applicant: IBM

Inventor： AICHELMANN JR ,  LANGE LAWRENCE K

IPC: G06F11/10 ,  G06F12/16 ,  G11C29/00 ,  G06F11/00

公开(公告)号：CA990355A

公开(公告)日：1976-06-01

申请号：CA171095

申请日：1973-05-02

Applicant: IBM

Inventor： CHAO CHESTER C ,  LANGE LAWRENCE K ,  LINDBLOOM ERIC ,  SAVKAR ANIL D

IPC: G06F11/22 ,  G01R31/28 ,  G01R31/3183 ,  G06F17/50 ,  H03K19/00

公开(公告)号：DE1169167B

公开(公告)日：1964-04-30

申请号：DEJ0021592

申请日：1962-04-11

Applicant: IBM

Inventor： ANNEY WILLIAM H MC ,  LANGE LAWRENCE K ,  GRUODIS ALGIRDAS J

IPC: G06F7/50 ,  G06F7/501 ,  H03K19/10

Abstract: 995,097. Transistor logic circuits. INTERNATIONAL BUSINESS MACHINES CORPORATION. March 28, 1962 [April 17, 1961], No. 11826/62. Heading H3T. [Also in Division G4] A switching circuit comprises a transistor 26, Fig. 1, having a negative resistance element 20 connected in its input circuit, the arrangement being such that with low or high voltage level input signals the element 20 is biased to high current values t 1 , t 3 , Fig. 2, and with an intermediate voltage level input signal it is biased to a low current value t 2 . The transistor 25 is switched to one state by the high current states, and to a second by the low current state. As described, the circuit forms a Full Adder in which transistors 26, 28 are both cut off when no input signals are present at A, B, C. Application of a signal to one input opens its associated gate 35-37, connecting the position supply 38, and the tunnel diode 20 conducts at operating point t 1 , Fig. 2, switching on transistor 26. Application of a second input moves the operating point of the tunnel diode to t 2 cutting transistor 26 off again and switching on transistor 28. With three inputs present, the operating point of the tunnel diode moves to t 3 and both transistors conduct. If the transistor 28 and constitutes a PARITY or EXCLUSIVE OR its associated resistors are omitted, the circuit circuit Fig. 4 (not shown).