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公开(公告)号：DE69322221T2
公开(公告)日：1999-07-01
申请号：DE69322221
申请日：1993-06-17
Applicant: IBM
Inventor： CHIN ARTHUR LIN , ELEAZAR-GARCIA SERAFIN J , LEE TIMOTHY VINCENT , KEENER DON STEVEN , MOORE GREGORY JAMES , STINE ERIC SPEESTRA
IPC: G06F13/362 , G06F13/36 , G06F13/38 , G06F13/364
Abstract: This invention relates to personal computers, and more particularly to a personal computer using a FIFO registers for data transfer as illustrated by a bus master device in the form of a small computer systems interface (SCSI) controller for controlling data transfer with storage memory devices such as fixed or removable media electromagnetic storage devices. In the practice of this invention, the efficiency of a system having a plurality of bus master devices is enhanced by providing for a programmable threshold fill condition for a FIFO register before arbitration for bus control occurs. Thus the invention provides an approach to maximizing the efficiency of data transfer where FIFO registers are used.
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公开(公告)号：DE69123769T2
公开(公告)日：1997-07-17
申请号：DE69123769
申请日：1991-02-25
Applicant: IBM
Inventor： FARRELL JOSEPH KEVIN , GORDON JEFFREY SCOTT , KUHL DANIEL C , LEE TIMOTHY VINCENT , PARKER TONY EDWIN
Abstract: An improved data link control device for use in high speed data communication applications, for instance primary rate ISDN applications, includes facilities for dynamic HyperChannel mapping. In such mapping, plural communication channels which ordinarily could be used for separate communication applications are associated as a HyperChannel group, and data communication is carried out concurrently over all channels of the group so as to advantageously utilise the aggregate bandwidth of the group. The present mapping facilities comprise means for designating one channel in each mapped group as a reference channel for the group, means for associating all other channels in the group to the respective reference channel, means for storing control information relative to the respective reference channel, and means responsive to the control information for conducting a data communication operation through all of the grouped channels including the reference channel as if all of said channels constituted a single extended channel having a bandwidth equal to that of the reference channel multiplied by the number of channels in the group.
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公开(公告)号：AU7029491A
公开(公告)日：1991-09-19
申请号：AU7029491
申请日：1991-02-05
Applicant: IBM
Inventor： FARRELL JOSEPH KEVIN , GORDON JEFFREY SCOTT , JENNESS ROBERT V , KUHL DANIEL C , LEE TIMOTHY VINCENT , PARKER TONY EDWIN
Abstract: A single chip integrated data link control (IDLC) device provides full duplex data throughput and versatile protocol adaptation between variably configured time channels on a high speed TDM digital link (e.g. T-1 or T-3 line) and a host data processing system. The device can handle multiple channels of voice and varied protocol data traffic, and thereby is suited for use in primary rate ISDN (Integrated Services Digital Network) applications. Synchronous and asynchronous special purpose logic sections in the device respectively interface with the network and a bus extending to external processing systems. Logic in the synchronous section forms plural-stage receive and transmit processing pipelines relative to the network interface. A "resource manager" element (RSM) and time swap (TS) RAM memory operate to dynamically vary states in these pipelines in synchronism with channel time slots at the network interface, whereby each pipeline operates in multitasking mode to perform plural functions relative to each channel during each time slot. The device also includes integrated memory queues in which communication data and channel status information are stacked relative to the device interfaces. Capacities and modes of operation of these queues are selected to minimize effects on chip size, throughput and cost, while supporting operations in the synchronous section pipelines so that critical time dependencies between consecutive pipeline stages, and between the pipelines and external processors, are lessened.
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公开(公告)号：DE69132648D1
公开(公告)日：2001-08-09
申请号：DE69132648
申请日：1991-02-25
Applicant: IBM
Inventor： FARRELL JOSEPH KEVIN , GORDON JEFFREY SCOTT , KUHL DANIEL C , LEE TIMOTHY VINCENT
Abstract: A single chip integrated data link control (IDLC) device provides full duplex data throughput and versatile protocol adaptation between variably configured time channels on a high speed TDM digital link (e.g. T-1 or T-3 line) and a host data processing system. The device handles multiple channels of mixed voice and data traffic concurrently, and thereby is suited for use in primary rate ISDN (Integrated Services Digital Network) applications. Synchronous and asynchronous sections in the device respectively interface with the network and host system. Special purpose autonomous logic elements in the synchronous section form plural stage receive and transmit processing pipelines between the network and host interfaces. Such pipelines perform OSI Layer 2 processing tasks on data in HDLC channels. Each autonomous element comprises one or more state machine circuits having functional autonomy and reduced time dependence relative to other elements. A "resource manager" element (RSM) and time swap (TS) RAM memory operate to dynamically swap states of pipeline elements in synchronism with channel time slots at the network interface, whereby the pipeline stages operate as data buffering stages which perform multiple tasks during any slot. The device contains integrated memory queues in which communication data and channel event status information are stacked for asynchronous transfer. Capacities and modes of operation of these queues are selected to minimize effects on chip size, throughput and cost, while minimizing critical time dependencies between the device and host system. Device elements provide first and second non-interfering information transfer paths between the device and host system; one for exchanges of control/status information between the device and host, and the other for direct memory access transfers of communication data between the device and an external memory associated with the host.
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公开(公告)号：DE69131584D1
公开(公告)日：1999-10-14
申请号：DE69131584
申请日：1991-02-25
Applicant: IBM
Inventor： FARRELL JOSEPH KEVIN , GORDON JEFFREY SCOTT , KUHL DANIEL C , PARKER TONY EDWIN , LEE TIMOTHY VINCENT
Abstract: Subject burst time division multiplex interface connects circuits which perform "layer 1 (L1)" line control functions relative to a data communication network with devices which perform "Layer 2 (L2)" link control functions relative to the same network (L1 and L2 defined by OSI Specifications of the International Standards Organisation). The interface is characterised by presentation of bursts of readiness indicating pulses from the L1 circuit to the L2 device during each basic time division multiplex time slot. The pulses indicate readiness of the circuits for data bit exchange, and separate time overlapped bursts are sent to indicate readiness of the circuits to send and receive data bits. Each burst contains a varied number of pulses ranging from 0 to n (where n is greater than 2, and in the disclosed embodiment equals 8). The bursts are positioned in a window of time occupying a fraction of the slot interval close to the end of each slot. This allows the L2 device to perform state swapping operations during the remainder of the slot to prepare for burst exchanges with different network channels to which the slots are allocatable and to be able to devote maximum processing time to performance of L2 tasks required relative to the channels. The channels operate under various communication protocols (HDLC, LAP-D, clear/voice, etc.). Slot time spacings are variable by the L1 circuits to adjust to signalling conditions in the network.
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Patent Agency Ranking
公开(公告)号：DE69130714T2
公开(公告)日：1999-08-05
申请号：DE69130714
申请日：1991-02-25
Applicant: IBM
Inventor： FARRELL JOSEPH KEVIN , GORDON JEFFREY SCOTT , JENNESS ROBERT V , KUHL DANIEL C , LEE TIMOTHY VINCENT , PARKER TONY EDWIN
Abstract: A single chip integrated data link control (IDLC) device provides full duplex data throughput and versatile protocol adaptation between variably configured time channels on a high speed TDM digital link (e.g. T-1 or T-3 line) and a host data processing system. The device can handle multiple channels of voice and varied protocol data traffic, and thereby is suited for use in primary rate ISDN (Integrated Services Digital Network) applications. Synchronous and asynchronous special purpose logic sections in the device respectively interface with the network and a bus extending to external processing systems. Logic in the synchronous section forms plural-stage receive and transmit processing pipelines relative to the network interface. A "resource manager" element (RSM) and time swap (TS) RAM memory operate to dynamically vary states in these pipelines in synchronism with channel time slots at the network interface, whereby each pipeline operates in multitasking mode to perform plural functions relative to each channel during each time slot. The device also includes integrated memory queues in which communication data and channel status information are stacked relative to the device interfaces. Capacities and modes of operation of these queues are selected to minimize effects on chip size, throughput and cost, while supporting operations in the synchronous section pipelines so that critical time dependencies between consecutive pipeline stages, and between the pipelines and external processors, are lessened.
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公开(公告)号：AT173843T
公开(公告)日：1998-12-15
申请号：AT93304739
申请日：1993-06-17
Applicant: IBM
Inventor： CHIN ARTHUR LIN , ELEAZAR-GARCIA SERAFIN J JR , LEE TIMOTHY VINCENT , KEENER DON STEVEN , MOORE GREGORY JAMES , STINE ERIC SPEESTRA
IPC: G06F13/36 , G06F13/362 , G06F13/38 , G06F13/364
Abstract: This invention relates to personal computers, and more particularly to a personal computer using a FIFO registers for data transfer as illustrated by a bus master device in the form of a small computer systems interface (SCSI) controller for controlling data transfer with storage memory devices such as fixed or removable media electromagnetic storage devices. In the practice of this invention, the efficiency of a system having a plurality of bus master devices is enhanced by providing for a programmable threshold fill condition for a FIFO register before arbitration for bus control occurs. Thus the invention provides an approach to maximizing the efficiency of data transfer where FIFO registers are used.
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公开(公告)号：DE69132648T2
公开(公告)日：2002-04-25
申请号：DE69132648
申请日：1991-02-25
Applicant: IBM
Inventor： FARRELL JOSEPH KEVIN , GORDON JEFFREY SCOTT , KUHL DANIEL C , LEE TIMOTHY VINCENT
Abstract: A single chip integrated data link control (IDLC) device provides full duplex data throughput and versatile protocol adaptation between variably configured time channels on a high speed TDM digital link (e.g. T-1 or T-3 line) and a host data processing system. The device handles multiple channels of mixed voice and data traffic concurrently, and thereby is suited for use in primary rate ISDN (Integrated Services Digital Network) applications. Synchronous and asynchronous sections in the device respectively interface with the network and host system. Special purpose autonomous logic elements in the synchronous section form plural stage receive and transmit processing pipelines between the network and host interfaces. Such pipelines perform OSI Layer 2 processing tasks on data in HDLC channels. Each autonomous element comprises one or more state machine circuits having functional autonomy and reduced time dependence relative to other elements. A "resource manager" element (RSM) and time swap (TS) RAM memory operate to dynamically swap states of pipeline elements in synchronism with channel time slots at the network interface, whereby the pipeline stages operate as data buffering stages which perform multiple tasks during any slot. The device contains integrated memory queues in which communication data and channel event status information are stacked for asynchronous transfer. Capacities and modes of operation of these queues are selected to minimize effects on chip size, throughput and cost, while minimizing critical time dependencies between the device and host system. Device elements provide first and second non-interfering information transfer paths between the device and host system; one for exchanges of control/status information between the device and host, and the other for direct memory access transfers of communication data between the device and an external memory associated with the host.
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公开(公告)号：DE69123769D1
公开(公告)日：1997-02-06
申请号：DE69123769
申请日：1991-02-25
Applicant: IBM
Inventor： FARRELL JOSEPH KEVIN , GORDON JEFFREY SCOTT , KUHL DANIEL C , LEE TIMOTHY VINCENT , PARKER TONY EDWIN
Abstract: An improved data link control device for use in high speed data communication applications, for instance primary rate ISDN applications, includes facilities for dynamic HyperChannel mapping. In such mapping, plural communication channels which ordinarily could be used for separate communication applications are associated as a HyperChannel group, and data communication is carried out concurrently over all channels of the group so as to advantageously utilise the aggregate bandwidth of the group. The present mapping facilities comprise means for designating one channel in each mapped group as a reference channel for the group, means for associating all other channels in the group to the respective reference channel, means for storing control information relative to the respective reference channel, and means responsive to the control information for conducting a data communication operation through all of the grouped channels including the reference channel as if all of said channels constituted a single extended channel having a bandwidth equal to that of the reference channel multiplied by the number of channels in the group.
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公开(公告)号：BR9104956A
公开(公告)日：1992-06-23
申请号：BR9104956
申请日：1991-11-14
Applicant: IBM
Inventor： FARRELL JOSEPH KEVIN , GORDON JEFFREY SCOTT , KUHL DANIEL CLAIR , LEE TIMOTHY VINCENT
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