-
公开(公告)号：AT173843T
公开(公告)日：1998-12-15
申请号：AT93304739
申请日：1993-06-17
Applicant: IBM
Inventor： CHIN ARTHUR LIN , ELEAZAR-GARCIA SERAFIN J JR , LEE TIMOTHY VINCENT , KEENER DON STEVEN , MOORE GREGORY JAMES , STINE ERIC SPEESTRA
IPC: G06F13/36 , G06F13/362 , G06F13/38 , G06F13/364
Abstract: This invention relates to personal computers, and more particularly to a personal computer using a FIFO registers for data transfer as illustrated by a bus master device in the form of a small computer systems interface (SCSI) controller for controlling data transfer with storage memory devices such as fixed or removable media electromagnetic storage devices. In the practice of this invention, the efficiency of a system having a plurality of bus master devices is enhanced by providing for a programmable threshold fill condition for a FIFO register before arbitration for bus control occurs. Thus the invention provides an approach to maximizing the efficiency of data transfer where FIFO registers are used.
-
公开(公告)号：CA2066001C
公开(公告)日：1998-02-17
申请号：CA2066001
申请日：1992-04-14
Applicant: IBM
Inventor： KEENER DON STEVEN , MOORE GREGORY JAMES
Abstract: This invention relates to personal computers, and more particularly to a personal computer using a small computer systems interface (SCSI) controller coupled directly to the local processor bus for controlling data transfer with storage memory devices such as fixed or removable media electromagnetic storage devices. The storage controller in accordance with this invention has internal volatile memory for transitory storage of data being communicated to coupled volatile memory. It further has control drivers interposed between the internal volatile memory and external volatile memory for controlling communication of data to the external volatile memory, with an enable driver and an enable receiver enchained between the control drivers and a source of signals controlling data communication. The enchained driver and receiver are connected for issuing a write signal to the external volatile memory prior to enablement of data communication through the control drivers and for sustaining a control signal communicated to the control drivers for enabling data communication until after deactivation of the write signal.
-
公开(公告)号：DE69322221T2
公开(公告)日：1999-07-01
申请号：DE69322221
申请日：1993-06-17
Applicant: IBM
Inventor： CHIN ARTHUR LIN , ELEAZAR-GARCIA SERAFIN J , LEE TIMOTHY VINCENT , KEENER DON STEVEN , MOORE GREGORY JAMES , STINE ERIC SPEESTRA
IPC: G06F13/362 , G06F13/36 , G06F13/38 , G06F13/364
Abstract: This invention relates to personal computers, and more particularly to a personal computer using a FIFO registers for data transfer as illustrated by a bus master device in the form of a small computer systems interface (SCSI) controller for controlling data transfer with storage memory devices such as fixed or removable media electromagnetic storage devices. In the practice of this invention, the efficiency of a system having a plurality of bus master devices is enhanced by providing for a programmable threshold fill condition for a FIFO register before arbitration for bus control occurs. Thus the invention provides an approach to maximizing the efficiency of data transfer where FIFO registers are used.
-
Patent Agency Ranking
公开(公告)号：SG42889A1
公开(公告)日：1997-10-17
申请号：SG1996000446
申请日：1993-06-17
Applicant: IBM
Inventor： CHIN ARTHUR LIN , ELEAZAR-GARCIA SERAFIN J JR , LEE TIMOTHY VINCENT , KEENER DON STEVEN , MOORE GREGORY JAMES , STINE ERIC SPEESTRA
IPC: G06F13/362 , G06F13/36 , G06F13/38 , G06F13/364
Abstract: This invention relates to personal computers, and more particularly to a personal computer using a FIFO registers for data transfer as illustrated by a bus master device in the form of a small computer systems interface (SCSI) controller for controlling data transfer with storage memory devices such as fixed or removable media electromagnetic storage devices. In the practice of this invention, the efficiency of a system having a plurality of bus master devices is enhanced by providing for a programmable threshold fill condition for a FIFO register before arbitration for bus control occurs. Thus the invention provides an approach to maximizing the efficiency of data transfer where FIFO registers are used.
-
公开(公告)号：DE69322221D1
公开(公告)日：1999-01-07
申请号：DE69322221
申请日：1993-06-17
Applicant: IBM
Inventor： CHIN ARTHUR LIN , ELEAZAR-GARCIA SERAFIN J , LEE TIMOTHY VINCENT , KEENER DON STEVEN , MOORE GREGORY JAMES , STINE ERIC SPEESTRA
IPC: G06F13/362 , G06F13/36 , G06F13/38 , G06F13/364
Abstract: This invention relates to personal computers, and more particularly to a personal computer using a FIFO registers for data transfer as illustrated by a bus master device in the form of a small computer systems interface (SCSI) controller for controlling data transfer with storage memory devices such as fixed or removable media electromagnetic storage devices. In the practice of this invention, the efficiency of a system having a plurality of bus master devices is enhanced by providing for a programmable threshold fill condition for a FIFO register before arbitration for bus control occurs. Thus the invention provides an approach to maximizing the efficiency of data transfer where FIFO registers are used.
-
公开(公告)号：CA2065989C
公开(公告)日：1998-03-31
申请号：CA2065989
申请日：1992-04-14
Applicant: IBM
Inventor： KEENER DON STEVEN , VOORHEES RICHARD W , MOORE GREGORY JAMES
Abstract: This invention relates to personal computers, and more particularly to a personal computer using a small computer systems interface (SCSI) controller coupled directly to the local processor bus for controlling data transfer with storage memory devices such as fixed or removable media electromagnetic storage devices. The personal computer system has a high speed local processor data bus, at least one logical processor device coupled directly to the local processor bus and capable of signalling through the local processor bus an occurrence of the transfer of blocks of data, and a storage controller coupled directly to the local processor bus for regulating communications between the processor device and storage memory devices. The storage controller has a FIFO memory for transitory storage of blocks of data being exchanged with the local processor bus and is capable of signalling through the local processor bus the state of the FIFO memory. The processor device and storage controller cooperate for exchange of blocks of data between the local processor bus and FIFO memory when the FIFO memory has available one of data to be transferred and space for reception of data and for emptying of the FIFO memory through the local processor bus as necessary.
-
公开(公告)号：CA2099025C
公开(公告)日：1996-12-03
申请号：CA2099025
申请日：1993-06-23
Applicant: IBM
Inventor： CHIN ARTHUR LIN , ELEAZAR-GARCIA SERAFIN JOSE JR , LEE TIMOTHY VINCENT , KEENER DON STEVEN , MOORE GREGORY JAMES , STINE ERIC SPEESTRA
IPC: G06F13/36 , G06F13/362 , G06F13/38
Abstract: This invention relates to personal computers, and more particularly to a personal computer using a FIFO registers for data transfer as illustrated by a bus master device in the form of a small computer systems interface (SCSI) controller for controlling data transfer with storage memory devices such as fixed or removable media electromagnetic storage devices. In the practice of this invention, the efficiency of a system having a plurality of bus master devices is enhanced by providing for a programmable threshold fill condition for a FIFO register before arbitration for bus control occurs. Thus the invention provides an approach to maximizing the efficiency of data transfer where FIFO registers are used.
-
公开(公告)号：CA2065991C
公开(公告)日：1996-01-02
申请号：CA2065991
申请日：1992-04-14
Applicant: IBM
Inventor： KEENER DON STEVEN , MOORE GREGORY JAMES
Abstract: This invention relates to personal computers, and more particularly to a personal computer using a small computer systems interface (SCSI) controller coupled directly to the local processor bus for controlling data transfer with storage memory devices such as fixed or removable media electromagnetic storage devices. The personal computer has a high speed local processor data bus and a storage controller coupled directly to said local processor bus for regulating communications between a processor and storage memory devices. The storage controller has at least one counter for tracking at least one of address and count data for blocks of data being transferred and capable of signalling through the local processor bus the state of the counter, and a bi-stable device interposed between the counter and the local processor bus for enabling delivery to the local processor bus of data representing an initial state of the counter at the beginning of a transfer of blocks of data and for continuing delivery of initial state data throughout a transfer of blocks of data. The counter and bi-stable device cooperate for permitting one of incrementing and decrementing of the counter during transfer of blocks of data while avoiding changes in counter state data delivered to the local processor bus during transfer of blocks of data.
-
-
-
-
-
-
-
Search Results
8
records
(took 0.018 seconds)
