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公开(公告)号：DE3364296D1
公开(公告)日：1986-08-07
申请号：DE3364296
申请日：1983-02-01
Applicant: IBM
Inventor： KRAFT WAYNE RICHARD , MOORE VICTOR STEWARD , PARKER TONY EDWIN , RHODES JOSEPH CULLEN , STAHL WILLIAM LEONARD , VENESKI GERARD ANTHONY
Abstract: A microword control system is provided for producing the sequences of microwords used to control the execution of processor instructions in a microprogrammed digital data processor. This microword control system includes a plurality of programmable logic array mechanisms responsive to the processor instruction to be executed for individually producing different ones of the microwords needed to execute such instruction. This microword control system also includes microword-responsive control circuitry for controlling the operation of the data processor. This microword control system further includes multiplexing circuitry for supplying microwords from different ones of the programmable logic array mechanisms to the control circuitry during different time intervals.
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公开(公告)号：DE69131584D1
公开(公告)日：1999-10-14
申请号：DE69131584
申请日：1991-02-25
Applicant: IBM
Inventor： FARRELL JOSEPH KEVIN , GORDON JEFFREY SCOTT , KUHL DANIEL C , PARKER TONY EDWIN , LEE TIMOTHY VINCENT
Abstract: Subject burst time division multiplex interface connects circuits which perform "layer 1 (L1)" line control functions relative to a data communication network with devices which perform "Layer 2 (L2)" link control functions relative to the same network (L1 and L2 defined by OSI Specifications of the International Standards Organisation). The interface is characterised by presentation of bursts of readiness indicating pulses from the L1 circuit to the L2 device during each basic time division multiplex time slot. The pulses indicate readiness of the circuits for data bit exchange, and separate time overlapped bursts are sent to indicate readiness of the circuits to send and receive data bits. Each burst contains a varied number of pulses ranging from 0 to n (where n is greater than 2, and in the disclosed embodiment equals 8). The bursts are positioned in a window of time occupying a fraction of the slot interval close to the end of each slot. This allows the L2 device to perform state swapping operations during the remainder of the slot to prepare for burst exchanges with different network channels to which the slots are allocatable and to be able to devote maximum processing time to performance of L2 tasks required relative to the channels. The channels operate under various communication protocols (HDLC, LAP-D, clear/voice, etc.). Slot time spacings are variable by the L1 circuits to adjust to signalling conditions in the network.
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公开(公告)号：DE69130714T2
公开(公告)日：1999-08-05
申请号：DE69130714
申请日：1991-02-25
Applicant: IBM
Inventor： FARRELL JOSEPH KEVIN , GORDON JEFFREY SCOTT , JENNESS ROBERT V , KUHL DANIEL C , LEE TIMOTHY VINCENT , PARKER TONY EDWIN
Abstract: A single chip integrated data link control (IDLC) device provides full duplex data throughput and versatile protocol adaptation between variably configured time channels on a high speed TDM digital link (e.g. T-1 or T-3 line) and a host data processing system. The device can handle multiple channels of voice and varied protocol data traffic, and thereby is suited for use in primary rate ISDN (Integrated Services Digital Network) applications. Synchronous and asynchronous special purpose logic sections in the device respectively interface with the network and a bus extending to external processing systems. Logic in the synchronous section forms plural-stage receive and transmit processing pipelines relative to the network interface. A "resource manager" element (RSM) and time swap (TS) RAM memory operate to dynamically vary states in these pipelines in synchronism with channel time slots at the network interface, whereby each pipeline operates in multitasking mode to perform plural functions relative to each channel during each time slot. The device also includes integrated memory queues in which communication data and channel status information are stacked relative to the device interfaces. Capacities and modes of operation of these queues are selected to minimize effects on chip size, throughput and cost, while supporting operations in the synchronous section pipelines so that critical time dependencies between consecutive pipeline stages, and between the pipelines and external processors, are lessened.
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公开(公告)号：DE69131584T2
公开(公告)日：2000-04-27
申请号：DE69131584
申请日：1991-02-25
Applicant: IBM
Inventor： FARRELL JOSEPH KEVIN , GORDON JEFFREY SCOTT , KUHL DANIEL C , PARKER TONY EDWIN , LEE TIMOTHY VINCENT
Abstract: Subject burst time division multiplex interface connects circuits which perform "layer 1 (L1)" line control functions relative to a data communication network with devices which perform "Layer 2 (L2)" link control functions relative to the same network (L1 and L2 defined by OSI Specifications of the International Standards Organisation). The interface is characterised by presentation of bursts of readiness indicating pulses from the L1 circuit to the L2 device during each basic time division multiplex time slot. The pulses indicate readiness of the circuits for data bit exchange, and separate time overlapped bursts are sent to indicate readiness of the circuits to send and receive data bits. Each burst contains a varied number of pulses ranging from 0 to n (where n is greater than 2, and in the disclosed embodiment equals 8). The bursts are positioned in a window of time occupying a fraction of the slot interval close to the end of each slot. This allows the L2 device to perform state swapping operations during the remainder of the slot to prepare for burst exchanges with different network channels to which the slots are allocatable and to be able to devote maximum processing time to performance of L2 tasks required relative to the channels. The channels operate under various communication protocols (HDLC, LAP-D, clear/voice, etc.). Slot time spacings are variable by the L1 circuits to adjust to signalling conditions in the network.
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Patent Agency Ranking
公开(公告)号：DE69130714D1
公开(公告)日：1999-02-18
申请号：DE69130714
申请日：1991-02-25
Applicant: IBM
Inventor： FARRELL JOSEPH KEVIN , GORDON JEFFREY SCOTT , JENNESS ROBERT V , KUHL DANIEL C , LEE TIMOTHY VINCENT , PARKER TONY EDWIN
Abstract: A single chip integrated data link control (IDLC) device provides full duplex data throughput and versatile protocol adaptation between variably configured time channels on a high speed TDM digital link (e.g. T-1 or T-3 line) and a host data processing system. The device can handle multiple channels of voice and varied protocol data traffic, and thereby is suited for use in primary rate ISDN (Integrated Services Digital Network) applications. Synchronous and asynchronous special purpose logic sections in the device respectively interface with the network and a bus extending to external processing systems. Logic in the synchronous section forms plural-stage receive and transmit processing pipelines relative to the network interface. A "resource manager" element (RSM) and time swap (TS) RAM memory operate to dynamically vary states in these pipelines in synchronism with channel time slots at the network interface, whereby each pipeline operates in multitasking mode to perform plural functions relative to each channel during each time slot. The device also includes integrated memory queues in which communication data and channel status information are stacked relative to the device interfaces. Capacities and modes of operation of these queues are selected to minimize effects on chip size, throughput and cost, while supporting operations in the synchronous section pipelines so that critical time dependencies between consecutive pipeline stages, and between the pipelines and external processors, are lessened.
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公开(公告)号：DE69123769T2
公开(公告)日：1997-07-17
申请号：DE69123769
申请日：1991-02-25
Applicant: IBM
Inventor： FARRELL JOSEPH KEVIN , GORDON JEFFREY SCOTT , KUHL DANIEL C , LEE TIMOTHY VINCENT , PARKER TONY EDWIN
Abstract: An improved data link control device for use in high speed data communication applications, for instance primary rate ISDN applications, includes facilities for dynamic HyperChannel mapping. In such mapping, plural communication channels which ordinarily could be used for separate communication applications are associated as a HyperChannel group, and data communication is carried out concurrently over all channels of the group so as to advantageously utilise the aggregate bandwidth of the group. The present mapping facilities comprise means for designating one channel in each mapped group as a reference channel for the group, means for associating all other channels in the group to the respective reference channel, means for storing control information relative to the respective reference channel, and means responsive to the control information for conducting a data communication operation through all of the grouped channels including the reference channel as if all of said channels constituted a single extended channel having a bandwidth equal to that of the reference channel multiplied by the number of channels in the group.
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公开(公告)号：AU7029491A
公开(公告)日：1991-09-19
申请号：AU7029491
申请日：1991-02-05
Applicant: IBM
Inventor： FARRELL JOSEPH KEVIN , GORDON JEFFREY SCOTT , JENNESS ROBERT V , KUHL DANIEL C , LEE TIMOTHY VINCENT , PARKER TONY EDWIN
Abstract: A single chip integrated data link control (IDLC) device provides full duplex data throughput and versatile protocol adaptation between variably configured time channels on a high speed TDM digital link (e.g. T-1 or T-3 line) and a host data processing system. The device can handle multiple channels of voice and varied protocol data traffic, and thereby is suited for use in primary rate ISDN (Integrated Services Digital Network) applications. Synchronous and asynchronous special purpose logic sections in the device respectively interface with the network and a bus extending to external processing systems. Logic in the synchronous section forms plural-stage receive and transmit processing pipelines relative to the network interface. A "resource manager" element (RSM) and time swap (TS) RAM memory operate to dynamically vary states in these pipelines in synchronism with channel time slots at the network interface, whereby each pipeline operates in multitasking mode to perform plural functions relative to each channel during each time slot. The device also includes integrated memory queues in which communication data and channel status information are stacked relative to the device interfaces. Capacities and modes of operation of these queues are selected to minimize effects on chip size, throughput and cost, while supporting operations in the synchronous section pipelines so that critical time dependencies between consecutive pipeline stages, and between the pipelines and external processors, are lessened.
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公开(公告)号：DE69123769D1
公开(公告)日：1997-02-06
申请号：DE69123769
申请日：1991-02-25
Applicant: IBM
Inventor： FARRELL JOSEPH KEVIN , GORDON JEFFREY SCOTT , KUHL DANIEL C , LEE TIMOTHY VINCENT , PARKER TONY EDWIN
Abstract: An improved data link control device for use in high speed data communication applications, for instance primary rate ISDN applications, includes facilities for dynamic HyperChannel mapping. In such mapping, plural communication channels which ordinarily could be used for separate communication applications are associated as a HyperChannel group, and data communication is carried out concurrently over all channels of the group so as to advantageously utilise the aggregate bandwidth of the group. The present mapping facilities comprise means for designating one channel in each mapped group as a reference channel for the group, means for associating all other channels in the group to the respective reference channel, means for storing control information relative to the respective reference channel, and means responsive to the control information for conducting a data communication operation through all of the grouped channels including the reference channel as if all of said channels constituted a single extended channel having a bandwidth equal to that of the reference channel multiplied by the number of channels in the group.
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公开(公告)号：DE3368778D1
公开(公告)日：1987-02-05
申请号：DE3368778
申请日：1983-02-01
Applicant: IBM
Inventor： PARKER TONY EDWIN , VENESKI GERARD ANTHONY
Abstract: The microcode control mechanism includes a sequence counter (18) for supplying a sequence of numbers, a programmable logic array (17) responsive to the processor instruction and to the sequence of numbers for producing a sequence of microwords needed to execute the instruction, a repeat circuitry (30, 31) responsive to a predetermined microword produced by the programmable logic array (17) for setting the sequence counter (18) back to a count which is less than the current count for causing a selected portion of the microword sequence to be repeated, and a programmable repeat counter (92) for counting the number of times the selected portion is repeated and for disabling the repeating action after a selected number of repeats.
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