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公开(公告)号：AT173843T
公开(公告)日：1998-12-15
申请号：AT93304739
申请日：1993-06-17
Applicant: IBM
Inventor： CHIN ARTHUR LIN , ELEAZAR-GARCIA SERAFIN J JR , LEE TIMOTHY VINCENT , KEENER DON STEVEN , MOORE GREGORY JAMES , STINE ERIC SPEESTRA
IPC: G06F13/36 , G06F13/362 , G06F13/38 , G06F13/364
Abstract: This invention relates to personal computers, and more particularly to a personal computer using a FIFO registers for data transfer as illustrated by a bus master device in the form of a small computer systems interface (SCSI) controller for controlling data transfer with storage memory devices such as fixed or removable media electromagnetic storage devices. In the practice of this invention, the efficiency of a system having a plurality of bus master devices is enhanced by providing for a programmable threshold fill condition for a FIFO register before arbitration for bus control occurs. Thus the invention provides an approach to maximizing the efficiency of data transfer where FIFO registers are used.
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公开(公告)号：CA2066001C
公开(公告)日：1998-02-17
申请号：CA2066001
申请日：1992-04-14
Applicant: IBM
Inventor： KEENER DON STEVEN , MOORE GREGORY JAMES
Abstract: This invention relates to personal computers, and more particularly to a personal computer using a small computer systems interface (SCSI) controller coupled directly to the local processor bus for controlling data transfer with storage memory devices such as fixed or removable media electromagnetic storage devices. The storage controller in accordance with this invention has internal volatile memory for transitory storage of data being communicated to coupled volatile memory. It further has control drivers interposed between the internal volatile memory and external volatile memory for controlling communication of data to the external volatile memory, with an enable driver and an enable receiver enchained between the control drivers and a source of signals controlling data communication. The enchained driver and receiver are connected for issuing a write signal to the external volatile memory prior to enablement of data communication through the control drivers and for sustaining a control signal communicated to the control drivers for enabling data communication until after deactivation of the write signal.
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公开(公告)号：DE69024111T2
公开(公告)日：1996-06-20
申请号：DE69024111
申请日：1990-06-11
Applicant: IBM
Inventor： DIXON JERRY DUANE , KEENER DON STEVEN , LOCKER HOWARD JEFFREY , MARAZAS GERALD ALLAN , MCNEILL ANDREW BOYCE , NEWSOM THOMAS HAROLD , OSBORN NEAL ALLEN
Abstract: Apparatus for assigning addresses to devices connected to an SCSI bus (10). A second configure bus (15) interconnects address assignable devices on the SCSI bus. The assignable devices may be used in a mixed system where some devices have fixed non-assignable addresses. The master device in the SCSI bus transmits configuration commands over the configuration bus and addresses for assignment over the SCSI bus. Acknowledgements are received back from a device which has accepted an address. Once configured with an address, the device propagates subsequent configuration commands to an adjacent device.
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公开(公告)号：AU623457B2
公开(公告)日：1992-05-14
申请号：AU4609089
申请日：1989-12-08
Applicant: IBM
Inventor： BUSH GREGORY FREDERICK , KEENER DON STEVEN , MOREL JEANNE ELLEN , VOORHEES RICHARD W
Abstract: In order to more effectively use read only memory space of a personal computer system, ROM code is selectively located or mapped to either an address boundary which is an even or odd integer multiple of one half the capacity of the read only memory device in which the ROM code is stored. The ROM code is stored in the read only memory device in two fields. In a first field, the ROM code is broken up into two segments, and the first segment precedes the second segment. In the second field, the same two segments are stored, but the second segment is stored preceding the first segment. A register, for storing page select bits, provides an input to an address decoder and an input to an adder, which adds unity to the contents of the register and provides its output to the address decoder as well. Accordingly, the address decoder will respond to either the page which is identified by the page select bits or the page following the identified page. The LSB of the page select bits is used in addressing the read only memory device to select between the first field (selected when the LSB is zero) or the second field (selected when the LSB is unity).
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Patent Agency Ranking
公开(公告)号：IN186098B
公开(公告)日：2001-06-16
申请号：IN363DE1993
申请日：1993-04-13
Applicant: IBM
Inventor： KEENER DON STEVEN , MCNEILL ANDREW BOYCE , NEWSOM THOMAS HAROLD , SCHEIERN KEVIN LEE , VOORHEES RICHARD W , WACHTEL EDWARD IRVING
IPC: G06F13/38
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公开(公告)号：DE69322221T2
公开(公告)日：1999-07-01
申请号：DE69322221
申请日：1993-06-17
Applicant: IBM
Inventor： CHIN ARTHUR LIN , ELEAZAR-GARCIA SERAFIN J , LEE TIMOTHY VINCENT , KEENER DON STEVEN , MOORE GREGORY JAMES , STINE ERIC SPEESTRA
IPC: G06F13/362 , G06F13/36 , G06F13/38 , G06F13/364
Abstract: This invention relates to personal computers, and more particularly to a personal computer using a FIFO registers for data transfer as illustrated by a bus master device in the form of a small computer systems interface (SCSI) controller for controlling data transfer with storage memory devices such as fixed or removable media electromagnetic storage devices. In the practice of this invention, the efficiency of a system having a plurality of bus master devices is enhanced by providing for a programmable threshold fill condition for a FIFO register before arbitration for bus control occurs. Thus the invention provides an approach to maximizing the efficiency of data transfer where FIFO registers are used.
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公开(公告)号：DE69026018T2
公开(公告)日：1996-10-02
申请号：DE69026018
申请日：1990-09-11
Applicant: IBM
Inventor： KEENER DON STEVEN , MCNEILL ANDREW BOYCE , WACHTEL EDWARD IRVING
IPC: G06F13/362 , G06F13/22 , G06F13/24 , G06F13/374
Abstract: Apparatus and method for increasing efficiency of command execution from a host processor (11) over an SCSI bus (14). Arbitration, selection and message out functions of SCSI protocol are implemented using a background arbitration state machine (32). Additional protocol functions are implemented in a foreground state machine (26). When the host processor (11) issues a command for access to the SCSI bus (14), the background state machine (32) can be programmed before the foreground machine (26) completes the protocol function for a previous command. Thus, the background state machine (32) is ready to arbitrate for access to the bus (14) at the very next bus free condition.
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公开(公告)号：DE3940302A1
公开(公告)日：1990-06-13
申请号：DE3940302
申请日：1989-12-06
Applicant: IBM
Inventor： BUSH GREGORY FREDERICK , KEENER DON STEVEN , MOREL JEANNE ELLEN , VOORHEES RICHARD
IPC: G06F12/06
Abstract: In order to more effectively use read only memory space of a personal computer system, ROM code is selectively located or mapped to either an address boundary which is an even or odd integer multiple of one half the capacity of the read only memory device in which the ROM code is stored. The ROM code is stored in the read only memory device in two fields. In a first field, the ROM code is broken up into two segments, and the first segment precedes the second segment. In the second field, the same two segments are stored, but the second segment is stored preceding the first segment. A register, for storing page select bits, provides an input to an address decoder and an input to an adder, which adds unity to the contents of the register and provides its output to the address decoder as well. Accordingly, the address decoder will respond to either the page which is identified by the page select bits or the page following the identified page. The LSB of the page select bits is used in addressing the read only memory device to select between the first field (selected when the LSB is zero) or the second field (selected when the LSB is unity).
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公开(公告)号：DE69322221D1
公开(公告)日：1999-01-07
申请号：DE69322221
申请日：1993-06-17
Applicant: IBM
Inventor： CHIN ARTHUR LIN , ELEAZAR-GARCIA SERAFIN J , LEE TIMOTHY VINCENT , KEENER DON STEVEN , MOORE GREGORY JAMES , STINE ERIC SPEESTRA
IPC: G06F13/362 , G06F13/36 , G06F13/38 , G06F13/364
Abstract: This invention relates to personal computers, and more particularly to a personal computer using a FIFO registers for data transfer as illustrated by a bus master device in the form of a small computer systems interface (SCSI) controller for controlling data transfer with storage memory devices such as fixed or removable media electromagnetic storage devices. In the practice of this invention, the efficiency of a system having a plurality of bus master devices is enhanced by providing for a programmable threshold fill condition for a FIFO register before arbitration for bus control occurs. Thus the invention provides an approach to maximizing the efficiency of data transfer where FIFO registers are used.
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