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    DYNAMIC RAM WITH ON-CHIP ECC AND OPTIMIZED BIT AND WORD REDUNDANCY
    1.
    发明专利
    DYNAMIC RAM WITH ON-CHIP ECC AND OPTIMIZED BIT AND WORD REDUNDANCY 未知

    公开(公告)号：CA2034027C

    公开(公告)日：1995-12-19

    申请号：CA2034027

    申请日：1991-01-11

    Applicant: IBM

    Inventor： BARTH JOHN E JR ,  DRAKE CHARLES E ,  FIFIELD JOHN A ,  HOVIS WILLIAM P ,  KALTER HOWARD L ,  LEWIS SCOTT C ,  NICKEL DANIEL J ,  STAPPER CHARLES H ,  YANKOSKY JAMES A

    IPC: G11C11/401 ,  G06F11/10 ,  G11C29/00 ,  G11C29/42 ,  G11C7/00

    Abstract: A DRAM having on-chip ECC and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides an any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a separate array section, and has been optimized to maximize signal while reducing soft errors. The array stores data in the form of error correction words (ECWs) on each word line. A first set of data lines (formed in a zig-zag pattern to minimize unequal capacitive loading on the underlying bit lines) are coupled to read out an ECW as well as the redundant bit lines. A second set of data lines receive the ECW as corrected by bit line redundancy, and a third set of data lines receive the ECW as corrected by the word line redundancy. The third set of data lines are coupled to the ECC block, which corrects errors encountered in the ECW. The ECC circuitry is optimized to reduce the access delays introduced by-carrying out on-chip error correction. The ECC block provides both the corrected data bits and the check bits to an SRAM. Thus, the check bits can be externally accessed, improving testability of the memory chip. At the same time, having a set of interrelated bits in the SRAM improves access performance when using multi-bit access modes, which compensates for whatever access delays are introduced by the ECC. To maximize the efficiency of switching from mode to mode, the modes are set as a function of received address signals.

    DYNAMIC RAM WITH ON-CHIP ECC AND OPTIMIZED BIT AND WORD REDUNDANCY
    2.
    发明专利
    DYNAMIC RAM WITH ON-CHIP ECC AND OPTIMIZED BIT AND WORD REDUNDANCY 未知

    公开(公告)号：CA2034027A1

    公开(公告)日：1991-08-14

    申请号：CA2034027

    申请日：1991-01-11

    Applicant: IBM

    Inventor： BARTH JOHN E JR ,  DRAKE CHARLES E ,  FIFIELD JOHN A ,  HOVIS WILLIAM P ,  KALTER HOWARD L ,  LEWIS SCOTT C ,  NICKEL DANIEL J ,  STAPPER CHARLES H ,  YANKOSKY JAMES A

    IPC: G11C11/401 ,  G06F11/10 ,  G11C29/00 ,  G11C29/42 ,  G11C7/00

    Abstract: A DRAM having on-chip ECC (30) and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides an any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a separate array section (20), and has been optimized to maximize signal while reducing soft errors. The array stores data in the form of error correction words (ECWs) on each word line. A first set of data lines (formed in a zig-zag pattern to minimize unequal capacitive loading on the underlying bit lines) are coupled to read out an ECW as well as the redundant bit lines. A second set of data lines receive the ECW as corrected by bit line redundancy, and a third set of data lines receive the ECW as corrected by the word line redundancy. The third set of data lines are coupled to the ECC block, which corrects errors encountered in the ECW. The ECC circuitry (30) is optimized to reduce the access delays introduced by carrying out on-chip error correction. The ECC block (30) provides both the corrected data bits and the check bits to an SRAM (40). Thus, the check bits can be externally accessed, improving testability of the memory chip. At the same time, having a set of interrelated bits in the SRAM (40) improves access performance when using multi-bit access modes, which compensates for whatever access delays are introduced by the ECC. To maximize the efficiency of switching from mode to mode, the modes are set as a function of received address signals.

    STORED CHARGE DIFFERENTIAL SENSE AMPLIFIER
    5.
    发明专利
    STORED CHARGE DIFFERENTIAL SENSE AMPLIFIER 未知

    公开(公告)号：CA1088668A

    公开(公告)日：1980-10-28

    申请号：CA265987

    申请日：1976-11-18

    Applicant: IBM

    Inventor： LEWIS SCOTT C

    IPC: G11C11/419 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4094 ,  H03K3/356 ,  G11C11/40

    Abstract: A differential sense amplifier for semiconductor memory cells is described which uses charge transfer preamplification in combination with a ratioless cross-coupled latch circuit to provide sensing and regeneration of binary information stored in a charge storage device. The sense amplifier may be utilized in arrays of single FET/capacitor memory cells in which the sense amplifier is centrally located and data input/output connections are made at one outside edge of the array. Single bit line driving is made possible by the use of a bit decoder which unconditionally couples charge to a single bit line and of common mode charge coupling to decrease potentials on a pair of bit lines coupled to the sense amplifier. The common mode bit line discharge means also increases response of the charge transfer preamplifier stage. A single transmission gate device is used for both reading out from a single bit line and writing new data back in, thus simplifying the input/output circuitry. A sense node shunting device is utilized during the bit line precharge portion of the memory cycle to partially charge the bit sense line previously discharged to ground in order to conserve power and to ensure proper operation of the charge transfer preamplifier on the next memory cycle. In semiconductor memory applications where high performance is critical, the charge transfer preamplifier stage and common mode discharging circuit may be omitted and the bit lines connected directly to the sense nodes of a cross-coupled latching circuit without the loss of other benefits of the circuit.

    CMOS DRIVER CIRCUIT
    6.
    发明专利
    CMOS DRIVER CIRCUIT 未知

    公开(公告)号：CA2024638C

    公开(公告)日：1995-04-25

    申请号：CA2024638

    申请日：1990-09-05

    Applicant: IBM

    Inventor： DRAKE CHARLES E ,  KALTER HOWARD L ,  LEWIS SCOTT C

    IPC: H03K17/687 ,  H03K17/04 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/0948

    Abstract: A CMOS integrated circuit for driving capacitance devices is provided. The circuit has an input node and an output node and includes a first transistor operatively connected to the input node which is turned "on" and "off" by the input node to supply an output signal to the output node when turned "on". A second transistor is provided, the output of which is connected to the output node when turned "on" to supply an output signal thereto. A control circuit is provided to turn on the first transistor prior to the second transistor, and to turn on the second transistor if and only if the slew rate of the output signal of the first transistor is less or slower than a given value. With this arrangement, if there is a low total capacitance of the capacitance devices being driven, the first transistor will have a fast enough slew rate that it will perform the entire charging function of the devices without turning on the second transistor; however, if the total capacitance of the devices being charged is sufficiently large, the low slew rate of the first transistor will cause the second transistor to be turned on, thereby providing additional charging voltage to the capacitance devices, thus decreasing the time that would be required if only the first transistor were employed for the entire charging.

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