公开(公告)号：EP1433179A4

公开(公告)日：2005-07-06

申请号：EP01995491

申请日：2001-12-10

Applicant: IBM

Inventor： BARTH JOHN E JR ,  PILO HAROLD

IPC: G11C11/407 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4091 ,  G11C11/4094 ,  G11C7/00

CPC classification number: G11C7/22 ,  G11C7/12 ,  G11C2207/104

Abstract: A system and method is disclosed for writing early within a memory cycle by holding only one of a true bitline (BTO) and a reference bitline (BC0) at a fixed potential, e.g. ground, when the sense amplifier (51) is set. The sense amplifier (51) amplifies a small voltage difference between the true bitline (BT0) and the reference bitline (BC0) to predetermined high and low voltage logic levels to write a datum to the memory cell. In this way, writing can complete in about the same time as reading, without risking corruption of data on adjacent bitlines in the memory. The bitlines are precharged to a fixed potential in a conduction path through the bitswitches (T1), rather than using local precharge devices at the sense amplifier (51). To write, bitswitches (T1) and writepath transistors (T3) apply the fixed potential to one of the true bitline (BT0) and the reference bitline (BC0). Bitswitches (T1) on such other memory cells not currently being written isolate the bitline coupled to those memory cells when setting the sense amplifiers, such that the stored contents of such memory cells not being written are refreshed (written back) at the time that the selected memory cell is written.

公开(公告)号：EP2371002A4

公开(公告)日：2012-12-12

申请号：EP09835439

申请日：2009-11-16

Applicant: IBM

Inventor： BARTH JOHN E JR

IPC: G11C11/4091 ,  G11C7/06

CPC classification number: G11C7/065 ,  G11C7/067 ,  G11C11/4091

公开(公告)号：CA2034027C

公开(公告)日：1995-12-19

申请号：CA2034027

申请日：1991-01-11

Applicant: IBM

Inventor： BARTH JOHN E JR ,  DRAKE CHARLES E ,  FIFIELD JOHN A ,  HOVIS WILLIAM P ,  KALTER HOWARD L ,  LEWIS SCOTT C ,  NICKEL DANIEL J ,  STAPPER CHARLES H ,  YANKOSKY JAMES A

IPC: G11C11/401 ,  G06F11/10 ,  G11C29/00 ,  G11C29/42 ,  G11C7/00

Abstract: A DRAM having on-chip ECC and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides an any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a separate array section, and has been optimized to maximize signal while reducing soft errors. The array stores data in the form of error correction words (ECWs) on each word line. A first set of data lines (formed in a zig-zag pattern to minimize unequal capacitive loading on the underlying bit lines) are coupled to read out an ECW as well as the redundant bit lines. A second set of data lines receive the ECW as corrected by bit line redundancy, and a third set of data lines receive the ECW as corrected by the word line redundancy. The third set of data lines are coupled to the ECC block, which corrects errors encountered in the ECW. The ECC circuitry is optimized to reduce the access delays introduced by-carrying out on-chip error correction. The ECC block provides both the corrected data bits and the check bits to an SRAM. Thus, the check bits can be externally accessed, improving testability of the memory chip. At the same time, having a set of interrelated bits in the SRAM improves access performance when using multi-bit access modes, which compensates for whatever access delays are introduced by the ECC. To maximize the efficiency of switching from mode to mode, the modes are set as a function of received address signals.

公开(公告)号：CA2034027A1

公开(公告)日：1991-08-14

申请号：CA2034027

申请日：1991-01-11

Applicant: IBM

Inventor： BARTH JOHN E JR ,  DRAKE CHARLES E ,  FIFIELD JOHN A ,  HOVIS WILLIAM P ,  KALTER HOWARD L ,  LEWIS SCOTT C ,  NICKEL DANIEL J ,  STAPPER CHARLES H ,  YANKOSKY JAMES A

IPC: G11C11/401 ,  G06F11/10 ,  G11C29/00 ,  G11C29/42 ,  G11C7/00

Abstract: A DRAM having on-chip ECC (30) and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides an any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a separate array section (20), and has been optimized to maximize signal while reducing soft errors. The array stores data in the form of error correction words (ECWs) on each word line. A first set of data lines (formed in a zig-zag pattern to minimize unequal capacitive loading on the underlying bit lines) are coupled to read out an ECW as well as the redundant bit lines. A second set of data lines receive the ECW as corrected by bit line redundancy, and a third set of data lines receive the ECW as corrected by the word line redundancy. The third set of data lines are coupled to the ECC block, which corrects errors encountered in the ECW. The ECC circuitry (30) is optimized to reduce the access delays introduced by carrying out on-chip error correction. The ECC block (30) provides both the corrected data bits and the check bits to an SRAM (40). Thus, the check bits can be externally accessed, improving testability of the memory chip. At the same time, having a set of interrelated bits in the SRAM (40) improves access performance when using multi-bit access modes, which compensates for whatever access delays are introduced by the ECC. To maximize the efficiency of switching from mode to mode, the modes are set as a function of received address signals.

公开(公告)号：AT327555T

公开(公告)日：2006-06-15

申请号：AT01995491

申请日：2001-12-10

Applicant: IBM

Inventor： BARTH JOHN E JR ,  PILO HAROLD

IPC: G11C11/407 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4091 ,  G11C11/4094 ,  G11C7/00

Abstract: A system and method is disclosed for writing early within a memory cycle by holding only one of a true bitline and a reference bitline at a fixed potential, e.g. ground, when the sense amplifier is set. The sense amplifier amplifies a small voltage difference between the true bitline and the reference bitline to predetermined high and low voltage logic levels to write a datum to the memory cell. In this way, writing can complete in about the same time as reading, without risking corruption of data on adjacent bitlines in the memory. The bitlines are precharged to a fixed potential in a conduction path through the bitswitches, rather than using local precharge devices at the sense amplifier. To write, bitswitches and write path transistors apply the fixed potential to one of the true bitline and the reference bitline. Bitswitches on such other memory cells not currently being written isolate the bitline pairs coupled to those memory cells when setting the sense amplifiers, such that the stored contents of such memory cells not being written are refreshed (written back) at the time that the selected memory cell is written.

公开(公告)号：MY123248A

公开(公告)日：2006-05-31

申请号：MYPI9904527

申请日：1999-10-20

Applicant: IBM

Inventor： BARTH JOHN E JR ,  BERTIN CLAUDE L ,  DREIBELBIS JEFFREY H ,  ELLIS WAYNE F ,  HOWELL WAYNE J ,  HEDBERG ERIK L ,  KALTER HOWARD LEO ,  TONTI WILLIAM R ,  WHEATER DONALD L

IPC: G11C29/00 ,  H01L21/66 ,  G01R31/28 ,  G01R31/319

Abstract: WAFER TEST AND BURN-IN IS ACCOMPLISHED WITH STATE MACHINE OR PROGRAMMABLE TEST ENGINES (29) LOCATED ON THE WAFER (26) BEING TESTED. EACH TEST ENGINE REQUIRE LESS THAN 10 CONNECTIONS AND EACH TEST ENGINE CAN BE CONNECTED TO A PLURALITY OF CHIPS (28-28", 28A-28E), SUCH AS A ROW OR A COLUMN OF CHIPS ON THE WAFER. THUS, THE NUMBER OF PADS (1-8) OF THE WAFER THAT MUST BE CONNECTED FOR TEST IS SUBSTANTIALLY REDUCED WHILE A LARGE DEGREE OF PARALLEL TESTING IS STILL PROVIDED. THE TEST ENGINES ALSO PERMIT ON-WAFER ALLOCATION OF REDUNDANCY IN PARALLEL SO THAT FAILING CHIPS CAN BE REPAIRED AFTER BURN-IN COMPLETE. IN ADDITION, THE PROGRAMMABLE TEST ENGINES CAN HAVE THEIR CODE ALTERED SO TEST PROGRAMS CAN BE MODIFIED TO ACCOUNT FOR NEW INFORMATION AFTER THE WAFER HAS BEEN FABRICATED. THE TEST ENGINES ARE USED DURING BURN-IN TO PROVIDE HIGH FREQUENCY WRITE SIGNALS TO DRAM ARRAYS THAT PROVIDE A HIGHER EFFECTIVE VOLTAGE TO THE ARRAYS, LOWERING THE TIME REQUIRED FOR BURN-IN. CONNECTIONS TO THE WAFER AND BETWEEN TEST ENGINES AND CHIPS ARE PROVIDED ALONG A MEMBERANE (20-20') ATTACHED TO THE WAFER. MEMBRANE CONNECTORS (31-31") CAN BE FORMED OR OPENED AFTER THE MEMBRANE IS CONNECTED TO THE WAFER SO SHORTED CHIPS CAN BE DISCONNECTED.PREFERABLY THE MEMBRANE REMAINS ON THE WAFER AFTER TEST, BURN-IN AND DICING TO PROVIDE A CHIP SCALE PACKAGE. THUS, THE VERY HIGH COST OF TCE MATCHED MATERIALS, SUCH AS GALSS CERAMIC CONTATCTORS, FOR WAFER BURN-IN IS AVOIDED WHILE PROVIDING BENEFIT BEYOND TEST AND BURN-IN FOR PACKAGING. (FIG. 2)