Driving method and circuit for pixel multiplexing circuits

    公开(公告)号:GB2344448A

    公开(公告)日:2000-06-07

    申请号:GB9925422

    申请日:1999-10-28

    Applicant: IBM

    Abstract: A driving method for multiplexing pixels in active matrix displays in accordance with the present invention includes the steps of providing a plurality of pixels arranged in an array, wherein each pixel includes at least two transistors associated therewith, the transistors disposed in the array of pixels and each pixel including a plurality of control lines for controlling the transistors for turning each pixel on and off and sequencing waveforms on the control lines to provide multiplexing at the pixels in the array. A circuit for addressing pixels in a pixel array in accordance with the present invention includes at least two transistors associated with each pixel, the transistors disposed in the array of pixels. A plurality of control lines associated with each pixel for controlling the transistors of each pixel. At least one gate driver sequences waveforms on the control lines to provide multiplexing at the pixels in the array.

    3.
    发明专利
    未知

    公开(公告)号:DE69411223T2

    公开(公告)日:1999-02-18

    申请号:DE69411223

    申请日:1994-04-13

    Applicant: IBM

    Abstract: The elimination of crosstalk between data lines and pixel cells in a thin film transistor/liquid crystal display is accomplished by applying a precharge voltage level for a given data signal level which also provides an equivalent to a compensation voltage for a prior scan line to a given data line for a time period less than the standard scan line period of the display, and applying the data signal to the given data line for the remainder of the scan line period.

    6.
    发明专利
    未知

    公开(公告)号:DE69411223D1

    公开(公告)日:1998-07-30

    申请号:DE69411223

    申请日:1994-04-13

    Applicant: IBM

    Abstract: The elimination of crosstalk between data lines and pixel cells in a thin film transistor/liquid crystal display is accomplished by applying a precharge voltage level for a given data signal level which also provides an equivalent to a compensation voltage for a prior scan line to a given data line for a time period less than the standard scan line period of the display, and applying the data signal to the given data line for the remainder of the scan line period.

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