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    METHOD AND SYSTEM FOR DECREASING POWER CONSUMPTION INSIDE ELECTRONIC CIRCUIT
    1.
    发明专利
    METHOD AND SYSTEM FOR DECREASING POWER CONSUMPTION INSIDE ELECTRONIC CIRCUIT 失效

    公开(公告)号：JPH10143297A

    公开(公告)日：1998-05-29

    申请号：JP26594297

    申请日：1997-09-30

    Applicant: IBM

    Inventor： LOPER ALBERT J ,  SUUMUYA MALIK

    IPC: G06F1/26 ,  G06F1/04 ,  G06F1/32 ,  G06F9/30 ,  G06F9/38 ,  G06F15/78

    Abstract: PROBLEM TO BE SOLVED: To reduce the power consumption inside an electronic circuit by respectively fetching a prescribed number of instructions from a memory for every cycle of a fetch circuit during the operation of the fetch circuit in 1st and 2nd power modes. SOLUTION: While the fetch circuit is operated in the 1st power mode, N (N is the integer of N>1) pieces of instructions are fetched at a maximum from the memory for every cycle of the fetch circuit. While the fetch circuit is operated in the 2nd power mode, M (M is the integer of N>M>0) pieces of instructions are fetched at a maximum from the memory for every cycle of the fetch circuit. When a special power mode is started, for example, a processor 10 decreases the maximum number of instructions to be fetched within a single cycle, changes the operation of an LSU 28 and decreases the number of 'ways' of an instruction cache 14 and a data cache 16 inside these caches so that the power consumption is reduced.

    Reducing power consumption in a processing device
    2.
    发明专利
    Reducing power consumption in a processing device 未知

    公开(公告)号：GB2317975A

    公开(公告)日：1998-04-08

    申请号：GB9716260

    申请日：1997-07-31

    Applicant: IBM

    Inventor： LOPER ALBERT J ,  MALLICK SOUMMYA

    IPC: G06F1/26 ,  G06F1/32 ,  G06F9/312 ,  G06F9/38 ,  G06F12/08 ,  G06F12/0864

    Abstract: If a processor 10 is operating in a 'full-power' mode, a load/store unit 28, executing a load instruction directed to floating-point registers 36, loads 64 bits of data from a data cache 16 into a rename buffer 38 during a single processor cycle. If, however, the processor is operating in a 'special' power mode, then the 64 bits are loaded over two cycles instead (i.e. 32 bits per cycle), halving the number of sense amplifiers active at a time in the cache and so saving power. The maximum number of instructions fetched per cycle from an instruction cache 14, decoded and dispatched to execution units 20, 22, 26, 28, and the number of cache ways active at a time, may also be halved in the 'special' power-saving mode.

    4.
    发明专利
    未知

    公开(公告)号：DE69636861T2

    公开(公告)日：2007-07-05

    申请号：DE69636861

    申请日：1996-08-29

    Applicant: IBM

    Inventor： KAHLE JAMES A ,  LOPER ALBERT J ,  MALLICK SOUMMYA ,  OGDEN AUBREY D

    IPC: G06F9/312 ,  G06F9/38 ,  G06F12/00

    Abstract: A load multiple instruction may be executed in a superscaler microprocessor by dispatching a load multiple instruction to a load/store unit, wherein the load/store unit begins execution of a dispatched load multiple instruction, and wherein the load multiple instruction loads data from memory into a plurality of registers. A table is maintained that lists each register of the plurality of registers and that indicates when data has been loaded into each register by the executing load multiple instruction. An instruction is executed that is dependent upon source operand data loaded by the load multiple instruction, prior to the load multiple instruction completing its execution, when the table indicates the source operand data has been loaded into the source register. Also, a store multiple instruction may be executed by dispatching a store multiple instruction to the load/store unit, whereupon the load/store unit begins executing the store multiple instruction, wherein the load/store instruction stores data from a plurality of registers to memory. A fixed point instruction is executed that is dependent upon data being stored by the store multiple instruction prior to the store multiple instruction completing its execution, but the executing fixed point instruction is prohibited from writing to a register of the plurality of registers prior to the store multiple instruction completing.

    5.
    发明专利
    未知

    公开(公告)号：DE69636861D1

    公开(公告)日：2007-03-15

    申请号：DE69636861

    申请日：1996-08-29

    Applicant: IBM

    Inventor： KAHLE JAMES A ,  LOPER ALBERT J ,  MALLICK SOUMMYA ,  OGDEN AUBREY D

    IPC: G06F9/312 ,  G06F9/38 ,  G06F12/00

    Abstract: A load multiple instruction may be executed in a superscaler microprocessor by dispatching a load multiple instruction to a load/store unit, wherein the load/store unit begins execution of a dispatched load multiple instruction, and wherein the load multiple instruction loads data from memory into a plurality of registers. A table is maintained that lists each register of the plurality of registers and that indicates when data has been loaded into each register by the executing load multiple instruction. An instruction is executed that is dependent upon source operand data loaded by the load multiple instruction, prior to the load multiple instruction completing its execution, when the table indicates the source operand data has been loaded into the source register. Also, a store multiple instruction may be executed by dispatching a store multiple instruction to the load/store unit, whereupon the load/store unit begins executing the store multiple instruction, wherein the load/store instruction stores data from a plurality of registers to memory. A fixed point instruction is executed that is dependent upon data being stored by the store multiple instruction prior to the store multiple instruction completing its execution, but the executing fixed point instruction is prohibited from writing to a register of the plurality of registers prior to the store multiple instruction completing.

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