中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

15 records (took 0.014 seconds)

    METHOD AND SYSTEM FOR INDEXING THE ASSIGNMENT OF INTERMEDIATE STORAGE BUFFERS IN A SUPERSCALAR PROCESSOR SYSTEM
    4.
    发明专利
    METHOD AND SYSTEM FOR INDEXING THE ASSIGNMENT OF INTERMEDIATE STORAGE BUFFERS IN A SUPERSCALAR PROCESSOR SYSTEM 未知

    公开(公告)号：CA2112995A1

    公开(公告)日：1994-07-09

    申请号：CA2112995

    申请日：1994-01-06

    Applicant: IBM

    Inventor： KAU CHIN-CHENG ,  OGDEN AUBREY D ,  WALDECKER DONALD E

    IPC: G06F9/38 ,  G06F9/30

    Abstract: METHOD AND SYSTEM FOR INDEXING THE ASSIGNMENT OF INTERMEDIATE STORAGE BUFFERS IN A SUPERSCALAR PROCESSOR SYSTEM A method and system for enhanced instruction dispatch efficiency in a superscalar processor system having a plurality of intermediate storage buffers, a plurality of general purpose registers, and a storage buffer index. Multiple scalar instructions may be simultaneously dispatched from a dispatch buffer to a plurality of execution units. Each of the multiple scalar instructions generally include at least one source operand and one destination operand. A particular one of the plurality of intermediate storage buffers is assigned to a destination operand within a selected one of the multiple scalar instructions. A relationship between the particular one of the plurality of intermediate storage buffers and a designated one of the plurality of general purpose registers is stored in the storage buffer index at that time when the instruction which has been dispatched is replaced in the dispatcher by another instruction in the application program sequence. Results of execution from the selected one of the multiple scalar instructions are stored in the particular one of the intermediate storage buffers when the selected instruction is executed. The storage buffer index is used to determine which storage buffers to use as source operands for those instructions which are dispatched between the time that a storage buffer has been assigned for a specific general purpose register and the results of execution are moved from the storage buffer into the general purpose register.

    6.
    发明专利
    未知

    公开(公告)号：DE69321929T2

    公开(公告)日：1999-07-01

    申请号：DE69321929

    申请日：1993-12-27

    Applicant: IBM

    Inventor： KAU CHIN-CHENG ,  OGDEN AUBREY D ,  WALDECKER DONALD E

    IPC: G06F9/38

    Abstract: A method and system for enhanced instruction dispatch efficiency in a superscalar processor system having intermediate storage buffers (60), general purpose registers (62), and a storage buffer index (58). A particular storage buffer (60) is assigned to a destination operand within a selected multiple scalar instruction. A relationship between the particular intermediate storage buffer (60) and a designated general purpose register (62) is stored in the storage buffer index (58) when the instruction which has been dispatched is replaced in the dispatcher by another instruction. Results of execution from the selected multiple scalar instruction are stored in the particular intermediate storage buffer (60) when the selected instruction is executed. The storage buffer index (58) is used to determine which storage buffers (60) to use as source operands for those instructions which are dispatched between the time that a storage buffer (58) has been assigned for a specific general purpose register (62) and the results of execution are moved from the storage buffer (60) into the general purpose register (62).

    7.
    发明专利
    未知

    公开(公告)号：AT173100T

    公开(公告)日：1998-11-15

    申请号：AT93120933

    申请日：1993-12-27

    Applicant: IBM

    Inventor： KAU CHIN-CHENG ,  OGDEN AUBREY D ,  WALDECKER DONALD E

    IPC: G06F9/38

    Abstract: A method and system for enhanced instruction dispatch efficiency in a superscalar processor system having intermediate storage buffers (60), general purpose registers (62), and a storage buffer index (58). A particular storage buffer (60) is assigned to a destination operand within a selected multiple scalar instruction. A relationship between the particular intermediate storage buffer (60) and a designated general purpose register (62) is stored in the storage buffer index (58) when the instruction which has been dispatched is replaced in the dispatcher by another instruction. Results of execution from the selected multiple scalar instruction are stored in the particular intermediate storage buffer (60) when the selected instruction is executed. The storage buffer index (58) is used to determine which storage buffers (60) to use as source operands for those instructions which are dispatched between the time that a storage buffer (58) has been assigned for a specific general purpose register (62) and the results of execution are moved from the storage buffer (60) into the general purpose register (62).

    8.
    发明专利
    未知

    公开(公告)号：DE69636861T2

    公开(公告)日：2007-07-05

    申请号：DE69636861

    申请日：1996-08-29

    Applicant: IBM

    Inventor： KAHLE JAMES A ,  LOPER ALBERT J ,  MALLICK SOUMMYA ,  OGDEN AUBREY D

    IPC: G06F9/312 ,  G06F9/38 ,  G06F12/00

    Abstract: A load multiple instruction may be executed in a superscaler microprocessor by dispatching a load multiple instruction to a load/store unit, wherein the load/store unit begins execution of a dispatched load multiple instruction, and wherein the load multiple instruction loads data from memory into a plurality of registers. A table is maintained that lists each register of the plurality of registers and that indicates when data has been loaded into each register by the executing load multiple instruction. An instruction is executed that is dependent upon source operand data loaded by the load multiple instruction, prior to the load multiple instruction completing its execution, when the table indicates the source operand data has been loaded into the source register. Also, a store multiple instruction may be executed by dispatching a store multiple instruction to the load/store unit, whereupon the load/store unit begins executing the store multiple instruction, wherein the load/store instruction stores data from a plurality of registers to memory. A fixed point instruction is executed that is dependent upon data being stored by the store multiple instruction prior to the store multiple instruction completing its execution, but the executing fixed point instruction is prohibited from writing to a register of the plurality of registers prior to the store multiple instruction completing.

    9.
    发明专利
    未知

    公开(公告)号：DE69636861D1

    公开(公告)日：2007-03-15

    申请号：DE69636861

    申请日：1996-08-29

    Applicant: IBM

    Inventor： KAHLE JAMES A ,  LOPER ALBERT J ,  MALLICK SOUMMYA ,  OGDEN AUBREY D

    IPC: G06F9/312 ,  G06F9/38 ,  G06F12/00

    Abstract: A load multiple instruction may be executed in a superscaler microprocessor by dispatching a load multiple instruction to a load/store unit, wherein the load/store unit begins execution of a dispatched load multiple instruction, and wherein the load multiple instruction loads data from memory into a plurality of registers. A table is maintained that lists each register of the plurality of registers and that indicates when data has been loaded into each register by the executing load multiple instruction. An instruction is executed that is dependent upon source operand data loaded by the load multiple instruction, prior to the load multiple instruction completing its execution, when the table indicates the source operand data has been loaded into the source register. Also, a store multiple instruction may be executed by dispatching a store multiple instruction to the load/store unit, whereupon the load/store unit begins executing the store multiple instruction, wherein the load/store instruction stores data from a plurality of registers to memory. A fixed point instruction is executed that is dependent upon data being stored by the store multiple instruction prior to the store multiple instruction completing its execution, but the executing fixed point instruction is prohibited from writing to a register of the plurality of registers prior to the store multiple instruction completing.

    10.
    发明专利
    未知

    公开(公告)号：DE69322064D1

    公开(公告)日：1998-12-17

    申请号：DE69322064

    申请日：1993-12-27

    Applicant: IBM

    Inventor： KAHLE JAMES A ,  KAU CHIN-CHENG ,  LEVITAN DAVID S ,  OGDEN AUBREY D ,  POURSEPANJ ALI A ,  KANG-GUO TU PAUL ,  WALDECKER DONALD E

    IPC: G06F9/38

    Abstract: A method and system for permitting single cycle instruction dispatch in a superscalar processor system which dispatches multiple instructions simultaneously to a group of execution units (24) for execution and placement of results thereof within specified general purpose registers (44, 46). Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers (40, 42) are provided and each time an instruction is dispatched to an available execution unit (24), a particular one of the intermediate storage buffers (40, 42) is assigned to any destination operand within the dispatched instruction, permitting the instruction to be dispatched within a single cycle by eliminating any requirement for determining and selecting the specified general purpose register (44, 46) or a designated alternate general purpose register.

Patent Agency Ranking