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    2.
    发明专利
    未知

    公开(公告)号：DE2523372A1

    公开(公告)日：1976-01-15

    申请号：DE2523372

    申请日：1975-05-27

    Applicant: IBM

    Inventor： KERRIGAN MICHAEL ,  LEBIZAY GERALD ,  MACSORLEY OLIN LOWE ,  WEISS ALFRED

    IPC: G06F13/36 ,  G06F13/34 ,  G06F3/04

    Abstract: An input-output port control subsystem for use with a computer system having separate source and destination buses incorporated therein. Said system including circuitry for controlling operations of said system and said input/output subsystem, said subsystem including a bidirectional input/output bus for transferring data to and from said system, and separate gating means for selectively connecting said source and destination buses to said bidirectional I/O bus. External devices are connected to said bus thru an adaptor unit which is directly connected to said processing system by appropriate control lines. The input/output subsystem is adapted to operate either under programmed I/O control mode thru the central processing system or in cycle steal mode wherein the I/O devices themselves request cycle steal service time on the I/O bus thru their connected adaptor.

    3.
    发明专利
    未知

    公开(公告)号：DE1263360B

    公开(公告)日：1968-03-14

    申请号：DEJ0030532

    申请日：1966-04-05

    Applicant: IBM

    Inventor： MACSORLEY OLIN LOWE

    IPC: G06F11/10

    Abstract: 1,082,588. Parity checking. INTERNATIONAL BUSINESS MACHINES CORPORATION. March 29, 1966 [April 5, 1965], No. 13803/66. Heading G4A. A data processor includes means for performing a parity check on a multi-byte word, each byte of which has an associated parity bit, when at least one data bit has been shifted between bytes or shifted from the word, said means being responsive to byte error signals. A multi-byte word, each byte having a parity bit, can be transferred from a first register to a second register with or without shift. In either case, a parity check is performed on each byte position of the second register (ignoring any change in byte boundaries) to produce respective error signals, which are fed to an OR gate and to an exclusive-or tree. A further input to the tree is " one " if the number of " one " bits shifted out (in the case of shift) is odd. A correct error signal is obtained from the OR gate or the tree in the case of no shift and shift respectively. Shift during multiplication and division is mentioned.

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